module clb(in, mux_in, clk, out, out_ff, program);

input wire [3:0] in;
input wire mux_in;
input wire program;
input wire clk;
output wire out;
output wire out_ff;

/* lut reg table
0 - 0000
1 - 0001
...
15 - 1111
*/

reg [15:0] lut;	// sram

assign out = lut[in];

always @(posedge clk) begin
	out_ff <= mux_in ? out : 1'bz;
end

endmodule