module clk_convert(clk, clk_out);

input wire clk;
output wire clk_out;

reg [17:0] counter;
reg clk_r=1'b0;

assign clk_out = clk_r;

// 200 Hz clk;
always @(posedge clk)
begin
	counter <= counter +18'b1;
	if (counter >= 18'd250000)
	begin
		counter <= 18'b0;
		clk_r <= ~clk_r;
	end
end

endmodule