/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.22 (git sha1 1979e0b, aarch64-linux-musl-c++ 10.2.1 -fstack-clash-protection -O2 -march=armv8-a -fdebug-prefix-map=/builddir/yosys-yosys-0.22=. -fPIC -Os) -- Parsing `eink_75.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: eink_75.v Parsing Verilog input from `eink_75.v' to AST representation. Storing AST representation for module `$abstract\clk_convert'. Storing AST representation for module `$abstract\eink_75'. Successfully finished Verilog frontend. -- Running command `synth_ice40' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Finding top of design hierarchy.. root of 0 design levels: $abstract\eink_75 root of 0 design levels: $abstract\clk_convert Automatically selected $abstract\eink_75 as design top module. 2.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\eink_75'. Generating RTLIL representation for module `\eink_75'. 2.2.3. Analyzing design hierarchy.. Top module: \eink_75 2.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\clk_convert'. Generating RTLIL representation for module `\clk_convert'. 2.2.5. Analyzing design hierarchy.. Top module: \eink_75 Used module: \clk_convert 2.2.6. Analyzing design hierarchy.. Top module: \eink_75 Used module: \clk_convert Removing unused module `$abstract\eink_75'. Removing unused module `$abstract\clk_convert'. Removed 2 unused modules. Mapping positional arguments of cell eink_75.CLK_CONVERT (clk_convert). 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. Marked 9 switch rules as full_case in process $proc$eink_75.v:60$381 in module eink_75. Removed a total of 0 dead cases. 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 8 redundant assignments. Promoted 38 assignments to connections. 2.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. Set init value: \Q = 1'0 Found init rule in `\clk_convert.$proc$clk_convert.v:7$411'. Set init value: \clk_r = 1'0 Found init rule in `\eink_75.$proc$eink_75.v:59$406'. Set init value: \powered = 1'0 Found init rule in `\eink_75.$proc$eink_75.v:52$405'. Set init value: \pushcount = 8'00000000 Found init rule in `\eink_75.$proc$eink_75.v:49$404'. Set init value: \datacounter = 20'00001111111111111111 Found init rule in `\eink_75.$proc$eink_75.v:23$403'. Set init value: \led2_r = 1'0 Found init rule in `\eink_75.$proc$eink_75.v:22$402'. Set init value: \led1_r = 1'0 2.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. Creating decoders for process `\clk_convert.$proc$clk_convert.v:7$411'. Creating decoders for process `\clk_convert.$proc$clk_convert.v:12$407'. 1/2: $0\counter[17:0] 2/2: $0\clk_r[0:0] Creating decoders for process `\eink_75.$proc$eink_75.v:59$406'. Creating decoders for process `\eink_75.$proc$eink_75.v:52$405'. Creating decoders for process `\eink_75.$proc$eink_75.v:49$404'. Creating decoders for process `\eink_75.$proc$eink_75.v:23$403'. Creating decoders for process `\eink_75.$proc$eink_75.v:22$402'. Creating decoders for process `\eink_75.$proc$eink_75.v:21$401'. Creating decoders for process `\eink_75.$proc$eink_75.v:60$381'. 1/46: $6\pushcount[7:0] 2/46: $9\push[7:0] 3/46: $4\din_r[0:0] 4/46: $6\datacounter[19:0] 5/46: $8\push[7:0] 6/46: $6\dc_r[0:0] 7/46: $6\frame[7679:0] 8/46: $5\datacounter[19:0] 9/46: $5\led2_r[0:0] 10/46: $7\push[7:0] 11/46: $5\dc_r[0:0] 12/46: $5\frame[7679:0] 13/46: $4\datacounter[19:0] 14/46: $6\push[7:0] 15/46: $4\dc_r[0:0] 16/46: $4\frame[7679:0] 17/46: $4\led2_r[0:0] 18/46: $5\push[7:0] 19/46: $3\datacounter[19:0] 20/46: $3\frame[7679:0] 21/46: $3\led2_r[0:0] 22/46: $3\dc_r[0:0] 23/46: $5\pushcount[7:0] 24/46: $3\din_r[0:0] 25/46: $2\datacounter[19:0] 26/46: $2\frame[7679:0] 27/46: $4\pushcount[7:0] 28/46: $4\push[7:0] 29/46: $2\led2_r[0:0] 30/46: $2\din_r[0:0] 31/46: $2\dc_r[0:0] 32/46: $3\led1_r[0:0] 33/46: $3\pushcount[7:0] 34/46: $3\push[7:0] 35/46: $2\led1_r[0:0] 36/46: $2\pushcount[7:0] 37/46: $2\push[7:0] 38/46: $1\powered[0:0] 39/46: $1\pushcount[7:0] 40/46: $1\push[7:0] 41/46: $1\led1_r[0:0] 42/46: $1\dc_r[0:0] 43/46: $1\datacounter[19:0] 44/46: $1\frame[7679:0] 45/46: $1\led2_r[0:0] 46/46: $1\din_r[0:0] 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\eink_75.\rst_r' from process `\eink_75.$proc$eink_75.v:21$401'. 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. created $adff cell `$procdff$880' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. created $dff cell `$procdff$881' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. created $adff cell `$procdff$882' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. created $dff cell `$procdff$883' with negative edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. created $adff cell `$procdff$884' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. created $dff cell `$procdff$885' with negative edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. created $adff cell `$procdff$886' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. created $dff cell `$procdff$887' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. created $dff cell `$procdff$888' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. created $dff cell `$procdff$889' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. created $adff cell `$procdff$890' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. created $dff cell `$procdff$891' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. created $adff cell `$procdff$892' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. created $dff cell `$procdff$893' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. created $adff cell `$procdff$894' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. created $dff cell `$procdff$895' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. created $adff cell `$procdff$896' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. created $dff cell `$procdff$897' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. created $dff cell `$procdff$898' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. created $dff cell `$procdff$899' with positive edge clock. Creating register for signal `\clk_convert.\counter' using process `\clk_convert.$proc$clk_convert.v:12$407'. created $dff cell `$procdff$900' with positive edge clock. Creating register for signal `\clk_convert.\clk_r' using process `\clk_convert.$proc$clk_convert.v:12$407'. created $dff cell `$procdff$901' with positive edge clock. Creating register for signal `\eink_75.\dc_r' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$902' with positive edge clock. Creating register for signal `\eink_75.\din_r' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$903' with positive edge clock. Creating register for signal `\eink_75.\led1_r' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$904' with positive edge clock. Creating register for signal `\eink_75.\led2_r' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$905' with positive edge clock. Creating register for signal `\eink_75.\frame' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$906' with positive edge clock. Creating register for signal `\eink_75.\datacounter' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$907' with positive edge clock. Creating register for signal `\eink_75.\push' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$908' with positive edge clock. Creating register for signal `\eink_75.\pushcount' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$909' with positive edge clock. Creating register for signal `\eink_75.\powered' using process `\eink_75.$proc$eink_75.v:60$381'. created $dff cell `$procdff$910' with positive edge clock. 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. Removing empty process `clk_convert.$proc$clk_convert.v:7$411'. Found and cleaned up 1 empty switch in `\clk_convert.$proc$clk_convert.v:12$407'. Removing empty process `clk_convert.$proc$clk_convert.v:12$407'. Removing empty process `eink_75.$proc$eink_75.v:59$406'. Removing empty process `eink_75.$proc$eink_75.v:52$405'. Removing empty process `eink_75.$proc$eink_75.v:49$404'. Removing empty process `eink_75.$proc$eink_75.v:23$403'. Removing empty process `eink_75.$proc$eink_75.v:22$402'. Removing empty process `eink_75.$proc$eink_75.v:21$401'. Found and cleaned up 9 empty switches in `\eink_75.$proc$eink_75.v:60$381'. Removing empty process `eink_75.$proc$eink_75.v:60$381'. Cleaned up 28 empty switches. 2.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module clk_convert. Optimizing module eink_75. 2.4. Executing FLATTEN pass (flatten design). Deleting now unused module clk_convert. 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 3 unused cells and 215 unused wires. 2.9. Executing CHECK pass (checking for obvious problems). Checking module eink_75... Found and reported 0 problems. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 1 cells. 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $procmux$464. dead port 2/2 on $mux $procmux$467. dead port 2/2 on $mux $procmux$470. dead port 1/2 on $mux $procmux$476. dead port 2/2 on $mux $procmux$479. dead port 2/2 on $mux $procmux$482. dead port 1/2 on $mux $procmux$488. dead port 2/2 on $mux $procmux$491. dead port 2/2 on $mux $procmux$494. dead port 1/2 on $mux $procmux$501. dead port 1/2 on $mux $procmux$504. dead port 2/2 on $mux $procmux$506. dead port 2/2 on $mux $procmux$509. dead port 2/2 on $mux $procmux$512. dead port 1/2 on $mux $procmux$519. dead port 1/2 on $mux $procmux$522. dead port 2/2 on $mux $procmux$524. dead port 2/2 on $mux $procmux$527. dead port 2/2 on $mux $procmux$530. dead port 1/2 on $mux $procmux$537. dead port 1/2 on $mux $procmux$540. dead port 2/2 on $mux $procmux$542. dead port 2/2 on $mux $procmux$545. dead port 2/2 on $mux $procmux$548. dead port 1/2 on $mux $procmux$555. dead port 1/2 on $mux $procmux$558. dead port 2/2 on $mux $procmux$560. dead port 2/2 on $mux $procmux$563. dead port 2/2 on $mux $procmux$566. dead port 1/2 on $mux $procmux$573. dead port 2/2 on $mux $procmux$575. dead port 2/2 on $mux $procmux$578. dead port 2/2 on $mux $procmux$581. dead port 1/2 on $mux $procmux$588. dead port 2/2 on $mux $procmux$590. dead port 2/2 on $mux $procmux$593. dead port 2/2 on $mux $procmux$596. dead port 1/2 on $mux $procmux$603. dead port 2/2 on $mux $procmux$605. dead port 2/2 on $mux $procmux$608. dead port 2/2 on $mux $procmux$611. dead port 1/2 on $mux $procmux$618. dead port 2/2 on $mux $procmux$620. dead port 2/2 on $mux $procmux$623. dead port 2/2 on $mux $procmux$626. dead port 1/2 on $mux $procmux$633. dead port 2/2 on $mux $procmux$635. dead port 2/2 on $mux $procmux$638. dead port 2/2 on $mux $procmux$641. dead port 2/2 on $mux $procmux$647. dead port 2/2 on $mux $procmux$650. dead port 2/2 on $mux $procmux$653. dead port 2/2 on $mux $procmux$659. dead port 2/2 on $mux $procmux$662. dead port 2/2 on $mux $procmux$665. dead port 2/2 on $mux $procmux$671. dead port 2/2 on $mux $procmux$674. dead port 2/2 on $mux $procmux$677. dead port 2/2 on $mux $procmux$683. dead port 2/2 on $mux $procmux$686. dead port 2/2 on $mux $procmux$689. dead port 2/2 on $mux $procmux$695. dead port 2/2 on $mux $procmux$698. dead port 2/2 on $mux $procmux$701. dead port 2/2 on $mux $procmux$707. dead port 2/2 on $mux $procmux$710. dead port 2/2 on $mux $procmux$716. dead port 2/2 on $mux $procmux$719. dead port 2/2 on $mux $procmux$725. dead port 2/2 on $mux $procmux$728. dead port 2/2 on $mux $procmux$734. dead port 2/2 on $mux $procmux$737. dead port 2/2 on $mux $procmux$743. dead port 2/2 on $mux $procmux$746. dead port 2/2 on $mux $procmux$752. dead port 2/2 on $mux $procmux$755. dead port 2/2 on $mux $procmux$761. dead port 2/2 on $mux $procmux$764. dead port 2/2 on $mux $procmux$770. dead port 2/2 on $mux $procmux$776. dead port 2/2 on $mux $procmux$782. dead port 2/2 on $mux $procmux$788. dead port 2/2 on $mux $procmux$794. dead port 2/2 on $mux $procmux$800. dead port 2/2 on $mux $procmux$806. dead port 2/2 on $mux $procmux$810. dead port 2/2 on $mux $procmux$813. dead port 1/2 on $mux $procmux$815. dead port 2/2 on $mux $procmux$819. dead port 2/2 on $mux $procmux$822. dead port 1/2 on $mux $procmux$824. dead port 2/2 on $mux $procmux$828. dead port 2/2 on $mux $procmux$831. dead port 1/2 on $mux $procmux$833. dead port 1/2 on $mux $procmux$839. dead port 1/2 on $mux $procmux$845. dead port 1/2 on $mux $procmux$851. Removed 97 multiplexer ports. 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Optimizing cells in module \eink_75. Performed a total of 1 changes. 2.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 0 unused cells and 99 unused wires. 2.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.10.16. Finished OPT passes. (There is nothing left to do.) 2.11. Executing FSM pass (extract and optimize FSM). 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $procdff$910 ($dff) from module eink_75 (D = $not$eink_75.v:77$385_Y, Q = \powered). Adding SRST signal on $procdff$909 ($dff) from module eink_75 (D = $4\pushcount[7:0], Q = \pushcount, rval = 8'11111111). Adding EN signal on $auto$ff.cc:266:slice$912 ($sdff) from module eink_75 (D = $5\pushcount[7:0], Q = \pushcount). Adding EN signal on $procdff$908 ($dff) from module eink_75 (D = $0\push[7:0], Q = \push). Adding EN signal on $procdff$907 ($dff) from module eink_75 (D = $2\datacounter[19:0], Q = \datacounter). Adding SRST signal on $auto$ff.cc:266:slice$925 ($dffe) from module eink_75 (D = $3\datacounter[19:0], Q = \datacounter, rval = 20'00000000000000000000). Adding EN signal on $procdff$906 ($dff) from module eink_75 (D = $2\frame[7679:0], Q = \frame). Adding SRST signal on $auto$ff.cc:266:slice$931 ($dffe) from module eink_75 (D = $3\frame[7679:0], Q = \frame, rval = 7680'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111). Adding EN signal on $procdff$905 ($dff) from module eink_75 (D = 1'1, Q = \led2_r). Adding EN signal on $procdff$904 ($dff) from module eink_75 (D = $2\led1_r[0:0], Q = \led1_r). Adding EN signal on $procdff$903 ($dff) from module eink_75 (D = \push [7], Q = \din_r). Adding SRST signal on $procdff$902 ($dff) from module eink_75 (D = $2\dc_r[0:0], Q = \dc_r, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$954 ($sdff) from module eink_75 (D = $4\dc_r[0:0], Q = \dc_r). Adding EN signal on $flatten\CLK_CONVERT.$procdff$901 ($dff) from module eink_75 (D = $flatten\CLK_CONVERT.$not$clk_convert.v:18$410_Y, Q = \CLK_CONVERT.clk_r). Adding SRST signal on $flatten\CLK_CONVERT.$procdff$900 ($dff) from module eink_75 (D = $flatten\CLK_CONVERT.$add$clk_convert.v:14$408_Y, Q = \CLK_CONVERT.counter, rval = 18'000000000000000000). 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 22 unused cells and 22 unused wires. 2.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 1 cells. 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 0 unused cells and 1 unused wires. 2.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.12.16. Rerunning OPT passes. (Maybe there is more to do..) 2.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.12.20. Executing OPT_DFF pass (perform DFF optimizations). 2.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.12.23. Finished OPT passes. (There is nothing left to do.) 2.13. Executing WREDUCE pass (reducing word size of cells). Removed top 17 bits (of 18) from port B of cell eink_75.$flatten\CLK_CONVERT.$add$clk_convert.v:14$408 ($add). Removed top 3 bits (of 16) from port B of cell eink_75.$le$eink_75.v:89$387 ($le). Removed top 4 bits (of 16) from port B of cell eink_75.$eq$eink_75.v:97$390 ($eq). Removed top 12 bits (of 16) from port B of cell eink_75.$add$eink_75.v:101$391 ($add). Removed top 3 bits (of 16) from port B of cell eink_75.$eq$eink_75.v:103$392 ($eq). Removed top 1 bits (of 2) from port B of cell eink_75.$auto$opt_dff.cc:195:make_patterns_logic$920 ($ne). Removed top 2 bits (of 4) from port B of cell eink_75.$auto$opt_dff.cc:195:make_patterns_logic$922 ($ne). Removed top 1 bits (of 2) from port B of cell eink_75.$auto$opt_dff.cc:195:make_patterns_logic$927 ($ne). Removed top 5 bits (of 8) from mux cell eink_75.$procmux$849 ($mux). Removed top 5 bits (of 8) from wire eink_75.$2\push[7:0]. 2.14. Executing PEEPOPT pass (run peephole optimizers). 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 0 unused cells and 1 unused wires. 2.16. Executing SHARE pass (SAT-based resource sharing). 2.17. Executing TECHMAP pass (map to technology primitives). 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.17.2. Continuing TECHMAP pass. No more expansions possible. 2.18. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module eink_75: creating $macc model for $add$eink_75.v:101$391 ($add). creating $macc model for $flatten\CLK_CONVERT.$add$clk_convert.v:14$408 ($add). creating $alu model for $macc $flatten\CLK_CONVERT.$add$clk_convert.v:14$408. creating $alu model for $macc $add$eink_75.v:101$391. creating $alu model for $flatten\CLK_CONVERT.$ge$clk_convert.v:15$409 ($ge): new $alu creating $alu model for $le$eink_75.v:89$387 ($le): new $alu creating $alu model for $eq$eink_75.v:103$392 ($eq): merged with $le$eink_75.v:89$387. creating $alu cell for $le$eink_75.v:89$387, $eq$eink_75.v:103$392: $auto$alumacc.cc:485:replace_alu$964 creating $alu cell for $flatten\CLK_CONVERT.$ge$clk_convert.v:15$409: $auto$alumacc.cc:485:replace_alu$977 creating $alu cell for $add$eink_75.v:101$391: $auto$alumacc.cc:485:replace_alu$990 creating $alu cell for $flatten\CLK_CONVERT.$add$clk_convert.v:14$408: $auto$alumacc.cc:485:replace_alu$993 created 4 $alu and 0 $macc cells. 2.21. Executing OPT pass (performing simple optimizations). 2.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$918 ($dffe) from module eink_75 (D = $4\push[7:0] [7:3], Q = \push [7:3], rval = 5'00000). 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 0 unused cells and 3 unused wires. 2.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.21.9. Rerunning OPT passes. (Maybe there is more to do..) 2.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.21.13. Executing OPT_DFF pass (perform DFF optimizations). 2.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.21.16. Finished OPT passes. (There is nothing left to do.) 2.22. Executing MEMORY pass. 2.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2.25. Executing TECHMAP pass (map to technology primitives). 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K_'. Successfully finished Verilog frontend. 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_SPRAM_'. Successfully finished Verilog frontend. 2.25.3. Continuing TECHMAP pass. No more expansions possible. 2.26. Executing ICE40_BRAMINIT pass. 2.27. Executing OPT pass (performing simple optimizations). 2.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 0 unused cells and 12 unused wires. 2.27.5. Finished fast OPT passes. 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.29. Executing OPT pass (performing simple optimizations). 2.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Consolidated identical input bits for $mux cell $procmux$849: Old ports: A=3'100, B=3'010, Y=$2\push[7:0] New ports: A=2'10, B=2'01, Y=$2\push[7:0] [2:1] New connections: $2\push[7:0] [0] = 1'0 Optimizing cells in module \eink_75. Performed a total of 1 changes. 2.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$930 ($sdffce) from module eink_75 (D = { $5\datacounter[19:0] [19:4] $5\datacounter[19:0] [2:0] }, Q = { \datacounter [19:4] \datacounter [2:0] }, rval = 19'0000000000000000000). 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.29.9. Rerunning OPT passes. (Maybe there is more to do..) 2.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.29.13. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$997 ($dffe) from module eink_75 (D = $7\push[7:0] [0], Q = \push [0], rval = 1'0). 2.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.29.16. Rerunning OPT passes. (Maybe there is more to do..) 2.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.29.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 1 cells. 2.29.20. Executing OPT_DFF pass (perform DFF optimizations). 2.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 0 unused cells and 1 unused wires. 2.29.22. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.29.23. Rerunning OPT passes. (Maybe there is more to do..) 2.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \eink_75.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \eink_75. Performed a total of 0 changes. 2.29.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.29.27. Executing OPT_DFF pass (perform DFF optimizations). 2.29.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.29.29. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.29.30. Finished OPT passes. (There is nothing left to do.) 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2.31. Executing TECHMAP pass (map to technology primitives). 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 2.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $not. Using template $paramod$18205a5da979f93ffab44671dcc4a48cf14e25e2\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $sdffce. Using template $paramod$c59fff10bfbf6a909195f2d154211eac024f754f\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using template $paramod$ea402187f386206c0840504755479bf827f47707\_80_ice40_alu for cells of type $alu. Using template $paramod$091610cd349a68bd5539cffd7126f0d76e9bca00\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $xor. No more expansions possible. 2.32. Executing OPT pass (performing simple optimizations). 2.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 6799 cells. 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 34 unused cells and 127 unused wires. 2.32.5. Finished fast OPT passes. 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2.33.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) eink_75.$auto$alumacc.cc:485:replace_alu$964.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$964.BB [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) eink_75.$auto$alumacc.cc:485:replace_alu$977.slice[0].carry: CO=\CLK_CONVERT.counter [4] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) eink_75.$auto$alumacc.cc:485:replace_alu$990.slice[0].carry: CO=\datacounter [3] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) eink_75.$auto$alumacc.cc:485:replace_alu$993.slice[0].carry: CO=\CLK_CONVERT.counter [0] 2.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 2 unused cells and 0 unused wires. 2.33.6. Rerunning OPT passes. (Removed registers in this run.) 2.33.7. Running ICE40 specific optimizations. 2.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.33.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.33.10. Executing OPT_DFF pass (perform DFF optimizations). 2.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.33.12. Finished OPT passes. (There is nothing left to do.) 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.35. Executing TECHMAP pass (map to technology primitives). 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.35.2. Continuing TECHMAP pass. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. No more expansions possible. 2.36. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping eink_75.$auto$alumacc.cc:485:replace_alu$990.slice[0].carry ($lut). Mapping eink_75.$auto$alumacc.cc:485:replace_alu$993.slice[0].carry ($lut). 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2.38.1. Running ICE40 specific optimizations. 2.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 985 cells. 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. Removed 0 unused cells and 7097 unused wires. 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 2.38.7. Running ICE40 specific optimizations. 2.38.8. Executing OPT_EXPR pass (perform const folding). Optimizing module eink_75. 2.38.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\eink_75'. Removed a total of 0 cells. 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \eink_75.. 2.38.12. Finished OPT passes. (There is nothing left to do.) 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. No more expansions possible. 2.40. Executing ABC pass (technology mapping using ABC). 2.40.1. Extracting gate netlist of module `\eink_75' to `/input.blif'.. Extracted 234 gates and 313 wires to a netlist network with 77 inputs and 70 outputs. 2.40.1.1. Executing ABC. Running ABC command: "abc" -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress /input.blif ABC: Total number of equiv classes = 72. ABC: Participating nodes from both networks = 189. ABC: Participating nodes from the first network = 73. ( 73.74 % of nodes) ABC: Participating nodes from the second network = 116. ( 117.17 % of nodes) ABC: Node pairs (any polarity) = 73. ( 73.74 % of names can be moved) ABC: Node pairs (same polarity) = 70. ( 70.71 % of names can be moved) ABC: Total runtime = 0.09 sec ABC: + write_blif /output.blif 2.40.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 98 ABC RESULTS: internal signals: 166 ABC RESULTS: input signals: 77 ABC RESULTS: output signals: 70 Removing temp directory. 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 2.42. Executing TECHMAP pass (map to technology primitives). 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.42.2. Continuing TECHMAP pass. No more expansions possible. Removed 34 unused cells and 211 unused wires. 2.43. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 131 1-LUT 23 2-LUT 39 3-LUT 41 4-LUT 28 with \SB_CARRY (#0) 31 with \SB_CARRY (#1) 32 Eliminating LUTs. Number of LUTs: 131 1-LUT 23 2-LUT 39 3-LUT 41 4-LUT 28 with \SB_CARRY (#0) 31 with \SB_CARRY (#1) 32 Combining LUTs. Number of LUTs: 115 1-LUT 23 2-LUT 22 3-LUT 27 4-LUT 43 with \SB_CARRY (#0) 31 with \SB_CARRY (#1) 32 Eliminated 0 LUTs. Combined 16 LUTs. 2.44. Executing TECHMAP pass (map to technology primitives). 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 2.44.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$9bfed69a345df7296febbc24dd2ff619a7c21a85\$lut for cells of type $lut. Using template $paramod$a59507d273cd827eb6c46c37820d50a1b717efdf\$lut for cells of type $lut. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$ea0faad69a26c91786a25961ea149d0e0961eb1f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut. Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut. Using template $paramod$d6cf0a4b6f6ccd87588da28c41b5b6c258da2509\$lut for cells of type $lut. Using template $paramod$e053a22d78e6bd5ea33183ea69976f0db741be0e\$lut for cells of type $lut. No more expansions possible. Removed 0 unused cells and 241 unused wires. 2.45. Executing AUTONAME pass. Renamed 4299 objects in module eink_75 (31 iterations). 2.46. Executing HIERARCHY pass (managing design hierarchy). 2.46.1. Analyzing design hierarchy.. Top module: \eink_75 2.46.2. Analyzing design hierarchy.. Top module: \eink_75 Removed 0 unused modules. 2.47. Printing statistics. === eink_75 === Number of wires: 89 Number of wire bits: 8064 Number of public wires: 89 Number of public wire bits: 8064 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 1197 SB_CARRY 63 SB_DFFE 6 SB_DFFESR 491 SB_DFFESS 504 SB_DFFSR 18 SB_LUT4 115 2.48. Executing CHECK pass (checking for obvious problems). Checking module eink_75... Found and reported 0 problems. -- Writing to `eink_75.json' using backend `json' -- 3. Executing JSON backend. End of script. Logfile hash: 72f3e1e0f6, CPU: user 852.95s system 60.16s, MEM: 233.47 MB peak Yosys 0.22 (git sha1 1979e0b, aarch64-linux-musl-c++ 10.2.1 -fstack-clash-protection -O2 -march=armv8-a -fdebug-prefix-map=/builddir/yosys-yosys-0.22=. -fPIC -Os) Time spent: 47% 21x opt_merge (432 sec), 23% 17x opt_dff (214 sec), ...