/----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.35 (git sha1 cc31c6e, aarch64-linux-musl-c++ 12.2.0 -fstack-clash-protection -O2 -march=armv8-a -ffile-prefix-map=/builddir/yosys-0.35=. -fPIC -Os) -- Parsing `rv30.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: rv30.v Parsing Verilog input from `rv30.v' to AST representation. Storing AST representation for module `$abstract\rv30'. Successfully finished Verilog frontend. -- Running command `synth_ice40' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Finding top of design hierarchy.. root of 0 design levels: $abstract\rv30 Automatically selected $abstract\rv30 as design top module. 2.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\rv30'. Generating RTLIL representation for module `\rv30'. Warning: Replacing memory \rvx with list of registers. See rv30.v:158, rv30.v:70, rv30.v:38 2.2.3. Analyzing design hierarchy.. Top module: \rv30 2.2.4. Analyzing design hierarchy.. Top module: \rv30 Removing unused module `$abstract\rv30'. Removed 1 unused modules. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. Removed 58 dead cases from process $proc$rv30.v:61$439 in module rv30. Marked 61 switch rules as full_case in process $proc$rv30.v:61$439 in module rv30. Removed a total of 58 dead cases. 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 8 redundant assignments. Promoted 155 assignments to connections. 2.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. Set init value: \Q = 1'0 Found init rule in `\rv30.$proc$rv30.v:35$975'. Set init value: \compute = 1'0 Found init rule in `\rv30.$proc$rv30.v:22$974'. Set init value: \pc = 0 2.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. Creating decoders for process `\rv30.$proc$rv30.v:35$975'. Creating decoders for process `\rv30.$proc$rv30.v:22$974'. Creating decoders for process `\rv30.$proc$rv30.v:61$439'. 1/841: $2\led_r[1:1] 2/841: $29\rvx[0][31:0] 3/841: $29\rvx[15][31:0] 4/841: $28\rvx[14][31:0] 5/841: $28\rvx[13][31:0] 6/841: $28\rvx[12][31:0] 7/841: $28\rvx[11][31:0] 8/841: $28\rvx[10][31:0] 9/841: $28\rvx[9][31:0] 10/841: $28\rvx[8][31:0] 11/841: $28\rvx[7][31:0] 12/841: $28\rvx[6][31:0] 13/841: $28\rvx[5][31:0] 14/841: $28\rvx[4][31:0] 15/841: $28\rvx[3][31:0] 16/841: $28\rvx[2][31:0] 17/841: $28\rvx[1][31:0] 18/841: $4$mem2reg_rd$\rvx$rv30.v:251$433_DATA[31:0]$970 19/841: $4$mem2reg_rd$\rvx$rv30.v:251$432_DATA[31:0]$969 20/841: $28\rvx[0][31:0] 21/841: $28\rvx[15][31:0] 22/841: $27\rvx[14][31:0] 23/841: $27\rvx[13][31:0] 24/841: $27\rvx[12][31:0] 25/841: $27\rvx[11][31:0] 26/841: $27\rvx[10][31:0] 27/841: $27\rvx[9][31:0] 28/841: $27\rvx[8][31:0] 29/841: $27\rvx[7][31:0] 30/841: $27\rvx[6][31:0] 31/841: $27\rvx[5][31:0] 32/841: $27\rvx[4][31:0] 33/841: $27\rvx[3][31:0] 34/841: $27\rvx[2][31:0] 35/841: $27\rvx[1][31:0] 36/841: $4$mem2reg_rd$\rvx$rv30.v:247$430_DATA[31:0]$966 37/841: $4$mem2reg_rd$\rvx$rv30.v:247$429_DATA[31:0]$965 38/841: $27\rvx[0][31:0] 39/841: $27\rvx[15][31:0] 40/841: $26\rvx[14][31:0] 41/841: $26\rvx[13][31:0] 42/841: $26\rvx[12][31:0] 43/841: $26\rvx[11][31:0] 44/841: $26\rvx[10][31:0] 45/841: $26\rvx[9][31:0] 46/841: $26\rvx[8][31:0] 47/841: $26\rvx[7][31:0] 48/841: $26\rvx[6][31:0] 49/841: $26\rvx[5][31:0] 50/841: $26\rvx[4][31:0] 51/841: $26\rvx[3][31:0] 52/841: $26\rvx[2][31:0] 53/841: $26\rvx[1][31:0] 54/841: $5$mem2reg_rd$\rvx$rv30.v:240$427_DATA[31:0]$962 55/841: $5$mem2reg_rd$\rvx$rv30.v:240$426_DATA[31:0]$961 56/841: $26\rvx[0][31:0] 57/841: $26\rvx[15][31:0] 58/841: $25\rvx[14][31:0] 59/841: $25\rvx[13][31:0] 60/841: $25\rvx[12][31:0] 61/841: $25\rvx[11][31:0] 62/841: $25\rvx[10][31:0] 63/841: $25\rvx[9][31:0] 64/841: $25\rvx[8][31:0] 65/841: $25\rvx[7][31:0] 66/841: $25\rvx[6][31:0] 67/841: $25\rvx[5][31:0] 68/841: $25\rvx[4][31:0] 69/841: $25\rvx[3][31:0] 70/841: $25\rvx[2][31:0] 71/841: $25\rvx[1][31:0] 72/841: $5$mem2reg_rd$\rvx$rv30.v:236$424_DATA[31:0]$958 73/841: $5$mem2reg_rd$\rvx$rv30.v:236$423_DATA[31:0]$957 74/841: $7\pc[31:0] 75/841: $25\rvx[15][31:0] 76/841: $24\rvx[14][31:0] 77/841: $24\rvx[13][31:0] 78/841: $24\rvx[12][31:0] 79/841: $24\rvx[11][31:0] 80/841: $24\rvx[10][31:0] 81/841: $24\rvx[9][31:0] 82/841: $24\rvx[8][31:0] 83/841: $24\rvx[7][31:0] 84/841: $24\rvx[6][31:0] 85/841: $24\rvx[5][31:0] 86/841: $24\rvx[4][31:0] 87/841: $24\rvx[3][31:0] 88/841: $24\rvx[2][31:0] 89/841: $24\rvx[1][31:0] 90/841: $25\rvx[0][31:0] 91/841: $4$mem2reg_wr$\rvx$rv30.v:236$422_ADDR[3:0]$945 92/841: $4$mem2reg_wr$\rvx$rv30.v:236$422_DATA[31:0]$946 93/841: $4$mem2reg_rd$\rvx$rv30.v:236$424_DATA[31:0]$950 94/841: $4$mem2reg_rd$\rvx$rv30.v:236$424_ADDR[3:0]$949 95/841: $4$mem2reg_rd$\rvx$rv30.v:236$423_DATA[31:0]$948 96/841: $4$mem2reg_rd$\rvx$rv30.v:236$423_ADDR[3:0]$947 97/841: $4$mem2reg_rd$\rvx$rv30.v:240$427_DATA[31:0]$956 98/841: $4$mem2reg_rd$\rvx$rv30.v:240$427_ADDR[3:0]$955 99/841: $4$mem2reg_rd$\rvx$rv30.v:240$426_DATA[31:0]$954 100/841: $4$mem2reg_rd$\rvx$rv30.v:240$426_ADDR[3:0]$953 101/841: $4$mem2reg_wr$\rvx$rv30.v:240$425_DATA[31:0]$952 102/841: $4$mem2reg_wr$\rvx$rv30.v:240$425_ADDR[3:0]$951 103/841: $24\rvx[0][31:0] 104/841: $24\rvx[15][31:0] 105/841: $23\rvx[14][31:0] 106/841: $23\rvx[13][31:0] 107/841: $23\rvx[12][31:0] 108/841: $23\rvx[11][31:0] 109/841: $23\rvx[10][31:0] 110/841: $23\rvx[9][31:0] 111/841: $23\rvx[8][31:0] 112/841: $23\rvx[7][31:0] 113/841: $23\rvx[6][31:0] 114/841: $23\rvx[5][31:0] 115/841: $23\rvx[4][31:0] 116/841: $23\rvx[3][31:0] 117/841: $23\rvx[2][31:0] 118/841: $23\rvx[1][31:0] 119/841: $4$mem2reg_rd$\rvx$rv30.v:230$421_DATA[31:0]$942 120/841: $4$mem2reg_rd$\rvx$rv30.v:230$420_DATA[31:0]$941 121/841: $23\rvx[0][31:0] 122/841: $23\rvx[15][31:0] 123/841: $22\rvx[14][31:0] 124/841: $22\rvx[13][31:0] 125/841: $22\rvx[12][31:0] 126/841: $22\rvx[11][31:0] 127/841: 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329/841: $15\rvx[4][31:0] 330/841: $15\rvx[3][31:0] 331/841: $15\rvx[2][31:0] 332/841: $15\rvx[1][31:0] 333/841: $5$mem2reg_rd$\rvx$rv30.v:192$403_DATA[31:0]$844 334/841: $5$mem2reg_rd$\rvx$rv30.v:192$402_DATA[31:0]$843 335/841: $15\rvx[0][31:0] 336/841: $15\rvx[15][31:0] 337/841: $14\rvx[14][31:0] 338/841: $14\rvx[13][31:0] 339/841: $14\rvx[12][31:0] 340/841: $14\rvx[11][31:0] 341/841: $14\rvx[10][31:0] 342/841: $14\rvx[9][31:0] 343/841: $14\rvx[8][31:0] 344/841: $14\rvx[7][31:0] 345/841: $14\rvx[6][31:0] 346/841: $14\rvx[5][31:0] 347/841: $14\rvx[4][31:0] 348/841: $14\rvx[3][31:0] 349/841: $14\rvx[2][31:0] 350/841: $14\rvx[1][31:0] 351/841: $5$mem2reg_rd$\rvx$rv30.v:188$400_DATA[31:0]$840 352/841: $5$mem2reg_rd$\rvx$rv30.v:188$399_DATA[31:0]$839 353/841: $4\pc[31:0] 354/841: $14\rvx[15][31:0] 355/841: $13\rvx[14][31:0] 356/841: $13\rvx[13][31:0] 357/841: $13\rvx[12][31:0] 358/841: $13\rvx[11][31:0] 359/841: $13\rvx[10][31:0] 360/841: $13\rvx[9][31:0] 361/841: $13\rvx[8][31:0] 362/841: $13\rvx[7][31:0] 363/841: $13\rvx[6][31:0] 364/841: $13\rvx[5][31:0] 365/841: $13\rvx[4][31:0] 366/841: $13\rvx[3][31:0] 367/841: $13\rvx[2][31:0] 368/841: $13\rvx[1][31:0] 369/841: $14\rvx[0][31:0] 370/841: $4$mem2reg_wr$\rvx$rv30.v:188$398_ADDR[3:0]$827 371/841: $4$mem2reg_wr$\rvx$rv30.v:188$398_DATA[31:0]$828 372/841: $4$mem2reg_rd$\rvx$rv30.v:188$400_DATA[31:0]$832 373/841: $4$mem2reg_rd$\rvx$rv30.v:188$400_ADDR[3:0]$831 374/841: $4$mem2reg_rd$\rvx$rv30.v:188$399_DATA[31:0]$830 375/841: $4$mem2reg_rd$\rvx$rv30.v:188$399_ADDR[3:0]$829 376/841: $4$mem2reg_rd$\rvx$rv30.v:192$403_DATA[31:0]$838 377/841: $4$mem2reg_rd$\rvx$rv30.v:192$403_ADDR[3:0]$837 378/841: $4$mem2reg_rd$\rvx$rv30.v:192$402_DATA[31:0]$836 379/841: $4$mem2reg_rd$\rvx$rv30.v:192$402_ADDR[3:0]$835 380/841: $4$mem2reg_wr$\rvx$rv30.v:192$401_DATA[31:0]$834 381/841: $4$mem2reg_wr$\rvx$rv30.v:192$401_ADDR[3:0]$833 382/841: $13\rvx[0][31:0] 383/841: $13\rvx[15][31:0] 384/841: $12\rvx[14][31:0] 385/841: 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492/841: $6\rvx[9][31:0] 493/841: $6\rvx[8][31:0] 494/841: $6\rvx[7][31:0] 495/841: $6\rvx[6][31:0] 496/841: $6\rvx[5][31:0] 497/841: $6\rvx[4][31:0] 498/841: $6\rvx[3][31:0] 499/841: $6\rvx[2][31:0] 500/841: $6\rvx[1][31:0] 501/841: $4$mem2reg_rd$\rvx$rv30.v:158$384_DATA[31:0]$804 502/841: $3\pc[31:0] 503/841: $6\rvx[15][31:0] 504/841: $5\rvx[14][31:0] 505/841: $5\rvx[13][31:0] 506/841: $5\rvx[12][31:0] 507/841: $5\rvx[11][31:0] 508/841: $5\rvx[10][31:0] 509/841: $5\rvx[9][31:0] 510/841: $5\rvx[8][31:0] 511/841: $5\rvx[7][31:0] 512/841: $5\rvx[6][31:0] 513/841: $5\rvx[5][31:0] 514/841: $5\rvx[4][31:0] 515/841: $5\rvx[3][31:0] 516/841: $5\rvx[2][31:0] 517/841: $5\rvx[1][31:0] 518/841: $6\rvx[0][31:0] 519/841: $3$mem2reg_wr$\rvx$rv30.v:158$383_ADDR[3:0]$762 520/841: $3$mem2reg_wr$\rvx$rv30.v:158$383_DATA[31:0]$763 521/841: $3$mem2reg_rd$\rvx$rv30.v:158$384_DATA[31:0]$765 522/841: $3$mem2reg_rd$\rvx$rv30.v:158$384_ADDR[3:0]$764 523/841: $3$mem2reg_rd$\rvx$rv30.v:192$403_DATA[31:0]$803 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$2$mem2reg_wr$\rvx$rv30.v:182$395_DATA[31:0]$682 689/841: $2$mem2reg_wr$\rvx$rv30.v:182$395_ADDR[3:0]$681 690/841: $2$mem2reg_rd$\rvx$rv30.v:178$394_DATA[31:0]$680 691/841: $2$mem2reg_rd$\rvx$rv30.v:178$394_ADDR[3:0]$679 692/841: $2$mem2reg_wr$\rvx$rv30.v:178$393_DATA[31:0]$678 693/841: $2$mem2reg_wr$\rvx$rv30.v:178$393_ADDR[3:0]$677 694/841: $2$mem2reg_rd$\rvx$rv30.v:174$392_DATA[31:0]$676 695/841: $2$mem2reg_rd$\rvx$rv30.v:174$392_ADDR[3:0]$675 696/841: $2$mem2reg_wr$\rvx$rv30.v:174$391_DATA[31:0]$674 697/841: $2$mem2reg_wr$\rvx$rv30.v:174$391_ADDR[3:0]$673 698/841: $2$mem2reg_rd$\rvx$rv30.v:170$390_DATA[31:0]$672 699/841: $2$mem2reg_rd$\rvx$rv30.v:170$390_ADDR[3:0]$671 700/841: $2$mem2reg_wr$\rvx$rv30.v:170$389_DATA[31:0]$670 701/841: $2$mem2reg_wr$\rvx$rv30.v:170$389_ADDR[3:0]$669 702/841: $2$mem2reg_rd$\rvx$rv30.v:166$388_DATA[31:0]$668 703/841: $2$mem2reg_rd$\rvx$rv30.v:166$388_ADDR[3:0]$667 704/841: $2$mem2reg_wr$\rvx$rv30.v:166$387_DATA[31:0]$666 705/841: $2$mem2reg_wr$\rvx$rv30.v:166$387_ADDR[3:0]$665 706/841: $2$mem2reg_rd$\rvx$rv30.v:162$386_DATA[31:0]$664 707/841: $2$mem2reg_rd$\rvx$rv30.v:162$386_ADDR[3:0]$663 708/841: $2$mem2reg_wr$\rvx$rv30.v:162$385_DATA[31:0]$662 709/841: $2$mem2reg_wr$\rvx$rv30.v:162$385_ADDR[3:0]$661 710/841: $2$mem2reg_rd$\rvx$rv30.v:158$384_DATA[31:0]$660 711/841: $2$mem2reg_rd$\rvx$rv30.v:158$384_ADDR[3:0]$659 712/841: $2$mem2reg_wr$\rvx$rv30.v:158$383_DATA[31:0]$658 713/841: $2$mem2reg_wr$\rvx$rv30.v:158$383_ADDR[3:0]$657 714/841: $2$mem2reg_wr$\rvx$rv30.v:75$382_DATA[31:0]$656 715/841: $2$mem2reg_wr$\rvx$rv30.v:75$382_ADDR[3:0]$655 716/841: $2\compute[0:0] 717/841: $1$mem2reg_rd$\rvx$rv30.v:251$433_DATA[31:0]$652 718/841: $1$mem2reg_rd$\rvx$rv30.v:251$433_ADDR[3:0]$651 719/841: $1$mem2reg_rd$\rvx$rv30.v:251$432_DATA[31:0]$650 720/841: $1$mem2reg_rd$\rvx$rv30.v:251$432_ADDR[3:0]$649 721/841: $1$mem2reg_wr$\rvx$rv30.v:251$431_DATA[31:0]$648 722/841: $1$mem2reg_wr$\rvx$rv30.v:251$431_ADDR[3:0]$647 723/841: $1$mem2reg_rd$\rvx$rv30.v:247$430_DATA[31:0]$646 724/841: $1$mem2reg_rd$\rvx$rv30.v:247$430_ADDR[3:0]$645 725/841: $1$mem2reg_rd$\rvx$rv30.v:247$429_DATA[31:0]$644 726/841: $1$mem2reg_rd$\rvx$rv30.v:247$429_ADDR[3:0]$643 727/841: $1$mem2reg_wr$\rvx$rv30.v:247$428_DATA[31:0]$642 728/841: $1$mem2reg_wr$\rvx$rv30.v:247$428_ADDR[3:0]$641 729/841: $1$mem2reg_rd$\rvx$rv30.v:240$427_DATA[31:0]$640 730/841: $1$mem2reg_rd$\rvx$rv30.v:240$427_ADDR[3:0]$639 731/841: $1$mem2reg_rd$\rvx$rv30.v:240$426_DATA[31:0]$638 732/841: $1$mem2reg_rd$\rvx$rv30.v:240$426_ADDR[3:0]$637 733/841: $1$mem2reg_wr$\rvx$rv30.v:240$425_DATA[31:0]$636 734/841: $1$mem2reg_wr$\rvx$rv30.v:240$425_ADDR[3:0]$635 735/841: $1$mem2reg_rd$\rvx$rv30.v:236$424_DATA[31:0]$634 736/841: $1$mem2reg_rd$\rvx$rv30.v:236$424_ADDR[3:0]$633 737/841: $1$mem2reg_rd$\rvx$rv30.v:236$423_DATA[31:0]$632 738/841: $1$mem2reg_rd$\rvx$rv30.v:236$423_ADDR[3:0]$631 739/841: $1$mem2reg_wr$\rvx$rv30.v:236$422_DATA[31:0]$630 740/841: $1$mem2reg_wr$\rvx$rv30.v:236$422_ADDR[3:0]$629 741/841: $1$mem2reg_rd$\rvx$rv30.v:230$421_DATA[31:0]$628 742/841: $1$mem2reg_rd$\rvx$rv30.v:230$421_ADDR[3:0]$627 743/841: $1$mem2reg_rd$\rvx$rv30.v:230$420_DATA[31:0]$626 744/841: $1$mem2reg_rd$\rvx$rv30.v:230$420_ADDR[3:0]$625 745/841: $1$mem2reg_wr$\rvx$rv30.v:230$419_DATA[31:0]$624 746/841: $1$mem2reg_wr$\rvx$rv30.v:230$419_ADDR[3:0]$623 747/841: $1$mem2reg_rd$\rvx$rv30.v:226$418_DATA[31:0]$622 748/841: $1$mem2reg_rd$\rvx$rv30.v:226$418_ADDR[3:0]$621 749/841: $1$mem2reg_rd$\rvx$rv30.v:226$417_DATA[31:0]$620 750/841: $1$mem2reg_rd$\rvx$rv30.v:226$417_ADDR[3:0]$619 751/841: $1$mem2reg_wr$\rvx$rv30.v:226$416_DATA[31:0]$618 752/841: $1$mem2reg_wr$\rvx$rv30.v:226$416_ADDR[3:0]$617 753/841: $1$mem2reg_rd$\rvx$rv30.v:222$415_DATA[31:0]$616 754/841: $1$mem2reg_rd$\rvx$rv30.v:222$415_ADDR[3:0]$615 755/841: $1$mem2reg_rd$\rvx$rv30.v:222$414_DATA[31:0]$614 756/841: $1$mem2reg_rd$\rvx$rv30.v:222$414_ADDR[3:0]$613 757/841: $1$mem2reg_wr$\rvx$rv30.v:222$413_DATA[31:0]$612 758/841: $1$mem2reg_wr$\rvx$rv30.v:222$413_ADDR[3:0]$611 759/841: $1$mem2reg_rd$\rvx$rv30.v:218$412_DATA[31:0]$610 760/841: $1$mem2reg_rd$\rvx$rv30.v:218$412_ADDR[3:0]$609 761/841: $1$mem2reg_rd$\rvx$rv30.v:218$411_DATA[31:0]$608 762/841: $1$mem2reg_rd$\rvx$rv30.v:218$411_ADDR[3:0]$607 763/841: $1$mem2reg_wr$\rvx$rv30.v:218$410_DATA[31:0]$606 764/841: $1$mem2reg_wr$\rvx$rv30.v:218$410_ADDR[3:0]$605 765/841: $1$mem2reg_rd$\rvx$rv30.v:211$409_DATA[31:0]$604 766/841: $1$mem2reg_rd$\rvx$rv30.v:211$409_ADDR[3:0]$603 767/841: $1$mem2reg_rd$\rvx$rv30.v:211$408_DATA[31:0]$602 768/841: $1$mem2reg_rd$\rvx$rv30.v:211$408_ADDR[3:0]$601 769/841: $1$mem2reg_wr$\rvx$rv30.v:211$407_DATA[31:0]$600 770/841: $1$mem2reg_wr$\rvx$rv30.v:211$407_ADDR[3:0]$599 771/841: $1$mem2reg_rd$\rvx$rv30.v:207$406_DATA[31:0]$598 772/841: $1$mem2reg_rd$\rvx$rv30.v:207$406_ADDR[3:0]$597 773/841: $1$mem2reg_rd$\rvx$rv30.v:207$405_DATA[31:0]$596 774/841: $1$mem2reg_rd$\rvx$rv30.v:207$405_ADDR[3:0]$595 775/841: $1$mem2reg_wr$\rvx$rv30.v:207$404_DATA[31:0]$594 776/841: $1$mem2reg_wr$\rvx$rv30.v:207$404_ADDR[3:0]$593 777/841: $1$mem2reg_rd$\rvx$rv30.v:192$403_DATA[31:0]$592 778/841: $1$mem2reg_rd$\rvx$rv30.v:192$403_ADDR[3:0]$591 779/841: $1$mem2reg_rd$\rvx$rv30.v:192$402_DATA[31:0]$590 780/841: $1$mem2reg_rd$\rvx$rv30.v:192$402_ADDR[3:0]$589 781/841: $1$mem2reg_wr$\rvx$rv30.v:192$401_DATA[31:0]$588 782/841: $1$mem2reg_wr$\rvx$rv30.v:192$401_ADDR[3:0]$587 783/841: $1$mem2reg_rd$\rvx$rv30.v:188$400_DATA[31:0]$586 784/841: $1$mem2reg_rd$\rvx$rv30.v:188$400_ADDR[3:0]$585 785/841: $1$mem2reg_rd$\rvx$rv30.v:188$399_DATA[31:0]$584 786/841: $1$mem2reg_rd$\rvx$rv30.v:188$399_ADDR[3:0]$583 787/841: $1$mem2reg_wr$\rvx$rv30.v:188$398_DATA[31:0]$582 788/841: $1$mem2reg_wr$\rvx$rv30.v:188$398_ADDR[3:0]$581 789/841: $1$mem2reg_rd$\rvx$rv30.v:182$397_DATA[31:0]$580 790/841: $1$mem2reg_rd$\rvx$rv30.v:182$397_ADDR[3:0]$579 791/841: $1$mem2reg_rd$\rvx$rv30.v:182$396_DATA[31:0]$578 792/841: $1$mem2reg_rd$\rvx$rv30.v:182$396_ADDR[3:0]$577 793/841: $1$mem2reg_wr$\rvx$rv30.v:182$395_DATA[31:0]$576 794/841: $1$mem2reg_wr$\rvx$rv30.v:182$395_ADDR[3:0]$575 795/841: $1$mem2reg_rd$\rvx$rv30.v:178$394_DATA[31:0]$574 796/841: $1$mem2reg_rd$\rvx$rv30.v:178$394_ADDR[3:0]$573 797/841: $1$mem2reg_wr$\rvx$rv30.v:178$393_DATA[31:0]$572 798/841: $1$mem2reg_wr$\rvx$rv30.v:178$393_ADDR[3:0]$571 799/841: $1$mem2reg_rd$\rvx$rv30.v:174$392_DATA[31:0]$570 800/841: $1$mem2reg_rd$\rvx$rv30.v:174$392_ADDR[3:0]$569 801/841: $1$mem2reg_wr$\rvx$rv30.v:174$391_DATA[31:0]$568 802/841: $1$mem2reg_wr$\rvx$rv30.v:174$391_ADDR[3:0]$567 803/841: $1$mem2reg_rd$\rvx$rv30.v:170$390_DATA[31:0]$566 804/841: $1$mem2reg_rd$\rvx$rv30.v:170$390_ADDR[3:0]$565 805/841: $1$mem2reg_wr$\rvx$rv30.v:170$389_DATA[31:0]$564 806/841: $1$mem2reg_wr$\rvx$rv30.v:170$389_ADDR[3:0]$563 807/841: $1$mem2reg_rd$\rvx$rv30.v:166$388_DATA[31:0]$562 808/841: $1$mem2reg_rd$\rvx$rv30.v:166$388_ADDR[3:0]$561 809/841: $1$mem2reg_wr$\rvx$rv30.v:166$387_DATA[31:0]$560 810/841: $1$mem2reg_wr$\rvx$rv30.v:166$387_ADDR[3:0]$559 811/841: $1$mem2reg_rd$\rvx$rv30.v:162$386_DATA[31:0]$558 812/841: $1$mem2reg_rd$\rvx$rv30.v:162$386_ADDR[3:0]$557 813/841: $1$mem2reg_wr$\rvx$rv30.v:162$385_DATA[31:0]$556 814/841: $1$mem2reg_wr$\rvx$rv30.v:162$385_ADDR[3:0]$555 815/841: $1$mem2reg_rd$\rvx$rv30.v:158$384_DATA[31:0]$554 816/841: $1$mem2reg_rd$\rvx$rv30.v:158$384_ADDR[3:0]$553 817/841: $1$mem2reg_wr$\rvx$rv30.v:158$383_DATA[31:0]$552 818/841: $1$mem2reg_wr$\rvx$rv30.v:158$383_ADDR[3:0]$551 819/841: $1$mem2reg_wr$\rvx$rv30.v:75$382_DATA[31:0]$550 820/841: $1$mem2reg_wr$\rvx$rv30.v:75$382_ADDR[3:0]$549 821/841: $1$mem2reg_wr$\rvx$rv30.v:70$381_DATA[31:0]$548 822/841: $1$mem2reg_wr$\rvx$rv30.v:70$381_ADDR[3:0]$547 823/841: $2\rvx[15][31:0] 824/841: $1\rvx[14][31:0] 825/841: $1\rvx[13][31:0] 826/841: $1\rvx[12][31:0] 827/841: $1\rvx[11][31:0] 828/841: $1\rvx[10][31:0] 829/841: $1\rvx[9][31:0] 830/841: $1\rvx[8][31:0] 831/841: $1\rvx[7][31:0] 832/841: $1\rvx[6][31:0] 833/841: $1\rvx[5][31:0] 834/841: $1\rvx[4][31:0] 835/841: $1\rvx[3][31:0] 836/841: $1\rvx[2][31:0] 837/841: $1\rvx[1][31:0] 838/841: $2\rvx[0][31:0] 839/841: $1\pc[31:0] 840/841: $1\opcode[4:0] 841/841: $1\led_r[1:1] Creating decoders for process `\rv30.$proc$rv30.v:37$436'. Creating decoders for process `\rv30.$proc$rv30.v:29$434'. 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. created $adff cell `$procdff$16376' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. created $dff cell `$procdff$16377' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. created $adff cell `$procdff$16378' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. created $dff cell `$procdff$16379' with negative edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. created $adff cell `$procdff$16380' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. created $dff cell `$procdff$16381' with negative edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. created $adff cell `$procdff$16382' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. created $dff cell `$procdff$16383' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. created $dff cell `$procdff$16384' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. created $dff cell `$procdff$16385' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. created $adff cell `$procdff$16386' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. created $dff cell `$procdff$16387' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. created $adff cell `$procdff$16388' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. created $dff cell `$procdff$16389' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. created $adff cell `$procdff$16390' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. created $dff cell `$procdff$16391' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. created $adff cell `$procdff$16392' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. created $dff cell `$procdff$16393' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. created $dff cell `$procdff$16394' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. created $dff cell `$procdff$16395' with positive edge clock. Creating register for signal `\rv30.\pc' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16396' with positive edge clock. Creating register for signal `\rv30.\led_r [1]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16397' with positive edge clock. Creating register for signal `\rv30.\compute' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16398' with positive edge clock. Creating register for signal `\rv30.\opcode' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16399' with positive edge clock. Creating register for signal `\rv30.\rvx[0]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16400' with positive edge clock. Creating register for signal `\rv30.\rvx[1]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16401' with positive edge clock. Creating register for signal `\rv30.\rvx[2]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16402' with positive edge clock. Creating register for signal `\rv30.\rvx[3]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16403' with positive edge clock. Creating register for signal `\rv30.\rvx[4]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16404' with positive edge clock. Creating register for signal `\rv30.\rvx[5]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16405' with positive edge clock. Creating register for signal `\rv30.\rvx[6]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16406' with positive edge clock. Creating register for signal `\rv30.\rvx[7]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16407' with positive edge clock. Creating register for signal `\rv30.\rvx[8]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16408' with positive edge clock. Creating register for signal `\rv30.\rvx[9]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16409' with positive edge clock. Creating register for signal `\rv30.\rvx[10]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16410' with positive edge clock. Creating register for signal `\rv30.\rvx[11]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16411' with positive edge clock. Creating register for signal `\rv30.\rvx[12]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16412' with positive edge clock. Creating register for signal `\rv30.\rvx[13]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16413' with positive edge clock. Creating register for signal `\rv30.\rvx[14]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16414' with positive edge clock. Creating register for signal `\rv30.\rvx[15]' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16415' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:70$381_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16416' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:70$381_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16417' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:75$382_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16418' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:75$382_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16419' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:158$383_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16420' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:158$383_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16421' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:158$384_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16422' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:158$384_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16423' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:162$385_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16424' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:162$385_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16425' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:162$386_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16426' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:162$386_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16427' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:166$387_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16428' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:166$387_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16429' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:166$388_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16430' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:166$388_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16431' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:170$389_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16432' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:170$389_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16433' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:170$390_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16434' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:170$390_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16435' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:174$391_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16436' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:174$391_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16437' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:174$392_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16438' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:174$392_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16439' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:178$393_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16440' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:178$393_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16441' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:178$394_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16442' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:178$394_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16443' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:182$395_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16444' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:182$395_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16445' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:182$396_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16446' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:182$396_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16447' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:182$397_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16448' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:182$397_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16449' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:188$398_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16450' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:188$398_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16451' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:188$399_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16452' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:188$399_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16453' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:188$400_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16454' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:188$400_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16455' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:192$401_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16456' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:192$401_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16457' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:192$402_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16458' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:192$402_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16459' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:192$403_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16460' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:192$403_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16461' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:207$404_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16462' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:207$404_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16463' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:207$405_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16464' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:207$405_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16465' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:207$406_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16466' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:207$406_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16467' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:211$407_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16468' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:211$407_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16469' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:211$408_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16470' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:211$408_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16471' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:211$409_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16472' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:211$409_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16473' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:218$410_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16474' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:218$410_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16475' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:218$411_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16476' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:218$411_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16477' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:218$412_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16478' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:218$412_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16479' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:222$413_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16480' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:222$413_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16481' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:222$414_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16482' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:222$414_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16483' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:222$415_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16484' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:222$415_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16485' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:226$416_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16486' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:226$416_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16487' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:226$417_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16488' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:226$417_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16489' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:226$418_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16490' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:226$418_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16491' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:230$419_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16492' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:230$419_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16493' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:230$420_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16494' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:230$420_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16495' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:230$421_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16496' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:230$421_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16497' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:236$422_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16498' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:236$422_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16499' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:236$423_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16500' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:236$423_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16501' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:236$424_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16502' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:236$424_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16503' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:240$425_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16504' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:240$425_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16505' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:240$426_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16506' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:240$426_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16507' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:240$427_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16508' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:240$427_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16509' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:247$428_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16510' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:247$428_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16511' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:247$429_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16512' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:247$429_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16513' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:247$430_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16514' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:247$430_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16515' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:251$431_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16516' with positive edge clock. Creating register for signal `\rv30.$mem2reg_wr$\rvx$rv30.v:251$431_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16517' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:251$432_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16518' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:251$432_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16519' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:251$433_ADDR' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16520' with positive edge clock. Creating register for signal `\rv30.$mem2reg_rd$\rvx$rv30.v:251$433_DATA' using process `\rv30.$proc$rv30.v:61$439'. created $dff cell `$procdff$16521' with positive edge clock. Creating register for signal `\rv30.\instr' using process `\rv30.$proc$rv30.v:37$436'. created $dff cell `$procdff$16522' with positive edge clock. Creating register for signal `\rv30.\compute' using process `\rv30.$proc$rv30.v:37$436'. created $dff cell `$procdff$16523' with positive edge clock. Creating register for signal `\rv30.\rvx[0]' using process `\rv30.$proc$rv30.v:37$436'. created $dff cell `$procdff$16524' with positive edge clock. Creating register for signal `\rv30.\rvx[15]' using process `\rv30.$proc$rv30.v:37$436'. created $dff cell `$procdff$16525' with positive edge clock. Creating register for signal `\rv30.\clk_div' using process `\rv30.$proc$rv30.v:29$434'. created $dff cell `$procdff$16526' with positive edge clock. 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. Removing empty process `rv30.$proc$rv30.v:35$975'. Removing empty process `rv30.$proc$rv30.v:22$974'. Found and cleaned up 61 empty switches in `\rv30.$proc$rv30.v:61$439'. Removing empty process `rv30.$proc$rv30.v:61$439'. Removing empty process `rv30.$proc$rv30.v:37$436'. Removing empty process `rv30.$proc$rv30.v:29$434'. Cleaned up 79 empty switches. 2.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.4. Executing FLATTEN pass (flatten design). 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. Removed 2063 unused cells and 4022 unused wires. 2.9. Executing CHECK pass (checking for obvious problems). Checking module rv30... Warning: multiple conflicting drivers for rv30.\rvx[15] [31]: port Q[31] of cell $procdff$16415 ($dff) port Q[31] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [30]: port Q[30] of cell $procdff$16415 ($dff) port Q[30] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [29]: port Q[29] of cell $procdff$16415 ($dff) port Q[29] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [28]: port Q[28] of cell $procdff$16415 ($dff) port Q[28] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [27]: port Q[27] of cell $procdff$16415 ($dff) port Q[27] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [26]: port Q[26] of cell $procdff$16415 ($dff) port Q[26] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [25]: port Q[25] of cell $procdff$16415 ($dff) port Q[25] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [24]: port Q[24] of cell $procdff$16415 ($dff) port Q[24] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [23]: port Q[23] of cell $procdff$16415 ($dff) port Q[23] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [22]: port Q[22] of cell $procdff$16415 ($dff) port Q[22] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [21]: port Q[21] of cell $procdff$16415 ($dff) port Q[21] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [20]: port Q[20] of cell $procdff$16415 ($dff) port Q[20] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [19]: port Q[19] of cell $procdff$16415 ($dff) port Q[19] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [18]: port Q[18] of cell $procdff$16415 ($dff) port Q[18] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [17]: port Q[17] of cell $procdff$16415 ($dff) port Q[17] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [16]: port Q[16] of cell $procdff$16415 ($dff) port Q[16] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [15]: port Q[15] of cell $procdff$16415 ($dff) port Q[15] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [14]: port Q[14] of cell $procdff$16415 ($dff) port Q[14] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [13]: port Q[13] of cell $procdff$16415 ($dff) port Q[13] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [12]: port Q[12] of cell $procdff$16415 ($dff) port Q[12] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [11]: port Q[11] of cell $procdff$16415 ($dff) port Q[11] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [10]: port Q[10] of cell $procdff$16415 ($dff) port Q[10] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [9]: port Q[9] of cell $procdff$16415 ($dff) port Q[9] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [8]: port Q[8] of cell $procdff$16415 ($dff) port Q[8] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [7]: port Q[7] of cell $procdff$16415 ($dff) port Q[7] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [6]: port Q[6] of cell $procdff$16415 ($dff) port Q[6] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [5]: port Q[5] of cell $procdff$16415 ($dff) port Q[5] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [4]: port Q[4] of cell $procdff$16415 ($dff) port Q[4] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [3]: port Q[3] of cell $procdff$16415 ($dff) port Q[3] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [2]: port Q[2] of cell $procdff$16415 ($dff) port Q[2] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [1]: port Q[1] of cell $procdff$16415 ($dff) port Q[1] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[15] [0]: port Q[0] of cell $procdff$16415 ($dff) port Q[0] of cell $procdff$16525 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [31]: port Q[31] of cell $procdff$16400 ($dff) port Q[31] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [30]: port Q[30] of cell $procdff$16400 ($dff) port Q[30] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [29]: port Q[29] of cell $procdff$16400 ($dff) port Q[29] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [28]: port Q[28] of cell $procdff$16400 ($dff) port Q[28] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [27]: port Q[27] of cell $procdff$16400 ($dff) port Q[27] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [26]: port Q[26] of cell $procdff$16400 ($dff) port Q[26] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [25]: port Q[25] of cell $procdff$16400 ($dff) port Q[25] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [24]: port Q[24] of cell $procdff$16400 ($dff) port Q[24] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [23]: port Q[23] of cell $procdff$16400 ($dff) port Q[23] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [22]: port Q[22] of cell $procdff$16400 ($dff) port Q[22] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [21]: port Q[21] of cell $procdff$16400 ($dff) port Q[21] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [20]: port Q[20] of cell $procdff$16400 ($dff) port Q[20] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [19]: port Q[19] of cell $procdff$16400 ($dff) port Q[19] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [18]: port Q[18] of cell $procdff$16400 ($dff) port Q[18] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [17]: port Q[17] of cell $procdff$16400 ($dff) port Q[17] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [16]: port Q[16] of cell $procdff$16400 ($dff) port Q[16] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [15]: port Q[15] of cell $procdff$16400 ($dff) port Q[15] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [14]: port Q[14] of cell $procdff$16400 ($dff) port Q[14] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [13]: port Q[13] of cell $procdff$16400 ($dff) port Q[13] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [12]: port Q[12] of cell $procdff$16400 ($dff) port Q[12] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [11]: port Q[11] of cell $procdff$16400 ($dff) port Q[11] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [10]: port Q[10] of cell $procdff$16400 ($dff) port Q[10] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [9]: port Q[9] of cell $procdff$16400 ($dff) port Q[9] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [8]: port Q[8] of cell $procdff$16400 ($dff) port Q[8] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [7]: port Q[7] of cell $procdff$16400 ($dff) port Q[7] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [6]: port Q[6] of cell $procdff$16400 ($dff) port Q[6] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [5]: port Q[5] of cell $procdff$16400 ($dff) port Q[5] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [4]: port Q[4] of cell $procdff$16400 ($dff) port Q[4] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [3]: port Q[3] of cell $procdff$16400 ($dff) port Q[3] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [2]: port Q[2] of cell $procdff$16400 ($dff) port Q[2] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [1]: port Q[1] of cell $procdff$16400 ($dff) port Q[1] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\rvx[0] [0]: port Q[0] of cell $procdff$16400 ($dff) port Q[0] of cell $procdff$16524 ($dff) Warning: multiple conflicting drivers for rv30.\compute: port Q[0] of cell $procdff$16398 ($dff) port Q[0] of cell $procdff$16523 ($dff) Found and reported 65 problems. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 7078 cells. 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $procmux$15999: \compute -> 1'0 Analyzing evaluation results. dead port 2/2 on $mux $procmux$3827. dead port 2/2 on $mux $procmux$5879. dead port 2/2 on $mux $procmux$3829. dead port 2/2 on $mux $procmux$2058. dead port 2/2 on $mux $procmux$12546. dead port 2/2 on $mux $procmux$11459. dead port 2/2 on $mux $procmux$14763. dead port 2/2 on $mux $procmux$14765. dead port 2/2 on $mux $procmux$11461. dead port 2/2 on $mux $procmux$10068. dead port 2/2 on $mux $procmux$11463. dead port 1/2 on $mux $procmux$5907. dead port 2/2 on $mux $procmux$5909. dead port 2/2 on $mux $procmux$13325. dead port 2/2 on $mux $procmux$5911. dead port 2/2 on $mux $procmux$5913. dead port 2/2 on $mux $procmux$13327. dead port 2/2 on $mux $procmux$11945. dead port 2/2 on $mux $procmux$13329. dead port 1/2 on $mux $procmux$2081. dead port 2/2 on $mux $procmux$2083. dead port 2/2 on $mux $procmux$1147. dead port 2/2 on $mux $procmux$2085. dead port 2/2 on $mux $procmux$11947. dead port 2/2 on $mux $procmux$2087. dead port 1/2 on $mux $procmux$5941. dead port 2/2 on $mux $procmux$5943. dead port 2/2 on $mux $procmux$11949. dead port 2/2 on $mux $procmux$5945. dead port 2/2 on $mux $procmux$10532. dead port 2/2 on $mux $procmux$5947. dead port 2/2 on $mux $procmux$1195. dead port 2/2 on $mux $procmux$14789. dead port 2/2 on $mux $procmux$14791. dead port 2/2 on $mux $procmux$10534. dead port 2/2 on $mux $procmux$10336. dead port 2/2 on $mux $procmux$10536. dead port 2/2 on $mux $procmux$12574. dead port 1/2 on $mux $procmux$5975. dead port 2/2 on $mux $procmux$5977. dead port 1/2 on $mux $procmux$2110. dead port 2/2 on $mux $procmux$5979. dead port 2/2 on $mux $procmux$2112. dead port 2/2 on $mux $procmux$5981. dead port 2/2 on $mux $procmux$2114. dead port 2/2 on $mux $procmux$12576. dead port 2/2 on $mux $procmux$2116. dead port 2/2 on $mux $procmux$12578. dead port 2/2 on $mux $procmux$10785. dead port 2/2 on $mux $procmux$3910. dead port 2/2 on $mux $procmux$13358. dead port 2/2 on $mux $procmux$3912. dead port 2/2 on $mux $procmux$3914. dead port 2/2 on $mux $procmux$10787. dead port 1/2 on $mux $procmux$6009. dead port 2/2 on $mux $procmux$6011. dead port 2/2 on $mux $procmux$13360. dead port 2/2 on $mux $procmux$6013. dead port 2/2 on $mux $procmux$10338. dead port 2/2 on $mux $procmux$6015. dead port 2/2 on $mux $procmux$14815. dead port 2/2 on $mux $procmux$13362. dead port 2/2 on $mux $procmux$14817. dead port 2/2 on $mux $procmux$1197. dead port 2/2 on $mux $procmux$10789. dead port 1/2 on $mux $procmux$2139. dead port 2/2 on $mux $procmux$2141. dead port 2/2 on $mux $procmux$2143. dead port 2/2 on $mux $procmux$10172. dead port 2/2 on $mux $procmux$2145. dead port 2/2 on $mux $procmux$3939. dead port 2/2 on $mux $procmux$3941. dead port 1/2 on $mux $procmux$6043. dead port 2/2 on $mux $procmux$6045. dead port 2/2 on $mux $procmux$6047. dead port 2/2 on $mux $procmux$3943. dead port 2/2 on $mux $procmux$6049. dead port 2/2 on $mux $procmux$11489. dead port 2/2 on $mux $procmux$11104. dead port 2/2 on $mux $procmux$11976. dead port 2/2 on $mux $procmux$1149. dead port 2/2 on $mux $procmux$11978. dead port 2/2 on $mux $procmux$10340. dead port 2/2 on $mux $procmux$11980. dead port 2/2 on $mux $procmux$11491. dead port 2/2 on $mux $procmux$1199. dead port 2/2 on $mux $procmux$12606. dead port 2/2 on $mux $procmux$11106. dead port 2/2 on $mux $procmux$12608. dead port 2/2 on $mux $procmux$14841. dead port 2/2 on $mux $procmux$11493. dead port 1/2 on $mux $procmux$2168. dead port 2/2 on $mux $procmux$3968. dead port 2/2 on $mux $procmux$2170. dead port 2/2 on $mux $procmux$3970. dead port 2/2 on $mux $procmux$14843. dead port 2/2 on $mux $procmux$3972. dead port 2/2 on $mux $procmux$2172. dead port 2/2 on $mux $procmux$2174. dead port 2/2 on $mux $procmux$12610. dead port 2/2 on $mux $procmux$11108. dead port 2/2 on $mux $procmux$10174. dead port 2/2 on $mux $procmux$3997. dead port 2/2 on $mux $procmux$3999. dead port 2/2 on $mux $procmux$10176. dead port 2/2 on $mux $procmux$4001. dead port 2/2 on $mux $procmux$13409. dead port 1/2 on $mux $procmux$2197. dead port 2/2 on $mux $procmux$2199. dead port 2/2 on $mux $procmux$2201. dead port 2/2 on $mux $procmux$6146. dead port 2/2 on $mux $procmux$6148. dead port 2/2 on $mux $procmux$2203. dead port 2/2 on $mux $procmux$6150. dead port 2/2 on $mux $procmux$6152. dead port 2/2 on $mux $procmux$14867. dead port 2/2 on $mux $procmux$13411. dead port 2/2 on $mux $procmux$14869. dead port 2/2 on $mux $procmux$4026. dead port 2/2 on $mux $procmux$4028. dead port 2/2 on $mux $procmux$4030. dead port 2/2 on $mux $procmux$12007. dead port 2/2 on $mux $procmux$12009. dead port 2/2 on $mux $procmux$6181. dead port 2/2 on $mux $procmux$6183. dead port 2/2 on $mux $procmux$6185. dead port 2/2 on $mux $procmux$12011. dead port 2/2 on $mux $procmux$6187. dead port 2/2 on $mux $procmux$13425. dead port 2/2 on $mux $procmux$12638. dead port 1/2 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2/2 on $mux $procmux$1834. dead port 2/2 on $mux $procmux$3545. dead port 2/2 on $mux $procmux$1836. dead port 2/2 on $mux $procmux$3547. dead port 2/2 on $mux $procmux$12416. dead port 2/2 on $mux $procmux$3549. dead port 2/2 on $mux $procmux$9299. dead port 2/2 on $mux $procmux$9301. dead port 2/2 on $mux $procmux$1838. dead port 2/2 on $mux $procmux$9303. dead port 2/2 on $mux $procmux$9305. dead port 2/2 on $mux $procmux$1072. dead port 2/2 on $mux $procmux$12418. dead port 2/2 on $mux $procmux$1049. dead port 2/2 on $mux $procmux$11017. dead port 2/2 on $mux $procmux$13160. dead port 2/2 on $mux $procmux$13162. dead port 2/2 on $mux $procmux$11019. dead port 2/2 on $mux $procmux$13164. dead port 2/2 on $mux $procmux$14612. dead port 2/2 on $mux $procmux$9328. dead port 2/2 on $mux $procmux$9330. dead port 2/2 on $mux $procmux$3573. dead port 2/2 on $mux $procmux$9332. dead port 2/2 on $mux $procmux$9334. dead port 2/2 on $mux $procmux$3575. dead port 2/2 on $mux $procmux$14614. dead port 2/2 on $mux $procmux$3577. dead port 2/2 on $mux $procmux$1860. dead port 2/2 on $mux $procmux$11021. dead port 2/2 on $mux $procmux$1862. dead port 2/2 on $mux $procmux$1864. dead port 2/2 on $mux $procmux$11852. dead port 2/2 on $mux $procmux$9357. dead port 2/2 on $mux $procmux$9359. dead port 2/2 on $mux $procmux$9361. dead port 2/2 on $mux $procmux$11854. dead port 2/2 on $mux $procmux$9363. dead port 2/2 on $mux $procmux$11856. dead port 1/2 on $mux $procmux$5533. dead port 2/2 on $mux $procmux$5535. dead port 2/2 on $mux $procmux$5537. dead port 2/2 on $mux $procmux$5539. dead port 2/2 on $mux $procmux$10728. dead port 2/2 on $mux $procmux$3601. dead port 2/2 on $mux $procmux$10145. dead port 2/2 on $mux $procmux$3603. dead port 2/2 on $mux $procmux$12446. dead port 2/2 on $mux $procmux$3605. dead port 2/2 on $mux $procmux$9386. dead port 2/2 on $mux $procmux$9388. dead port 2/2 on $mux $procmux$9390. dead port 2/2 on $mux $procmux$11399. dead port 2/2 on $mux $procmux$9392. dead port 2/2 on $mux $procmux$12448. dead port 2/2 on $mux $procmux$10730. dead port 2/2 on $mux $procmux$10308. dead port 2/2 on $mux $procmux$1886. dead port 2/2 on $mux $procmux$1245. dead port 2/2 on $mux $procmux$1888. dead port 2/2 on $mux $procmux$14637. dead port 2/2 on $mux $procmux$1890. dead port 1/2 on $mux $procmux$5567. dead port 2/2 on $mux $procmux$5569. dead port 2/2 on $mux $procmux$5571. dead port 2/2 on $mux $procmux$13193. dead port 2/2 on $mux $procmux$5573. dead port 2/2 on $mux $procmux$14639. dead port 2/2 on $mux $procmux$12450. dead port 2/2 on $mux $procmux$13195. dead port 2/2 on $mux $procmux$3629. dead port 2/2 on $mux $procmux$13197. dead port 2/2 on $mux $procmux$3631. dead port 2/2 on $mux $procmux$11401. dead port 2/2 on $mux $procmux$3633. dead port 2/2 on $mux $procmux$1320. dead port 2/2 on $mux $procmux$10732. dead port 2/2 on $mux $procmux$11403. dead port 1/2 on $mux $procmux$5601. dead port 2/2 on $mux $procmux$5603. dead port 2/2 on $mux $procmux$5605. dead port 2/2 on $mux $procmux$5607. dead port 2/2 on $mux $procmux$9458. dead port 2/2 on $mux $procmux$9460. dead port 2/2 on $mux $procmux$1074. dead port 2/2 on $mux $procmux$9462. dead port 2/2 on $mux $procmux$9470. dead port 2/2 on $mux $procmux$9472. dead port 2/2 on $mux $procmux$9474. dead port 2/2 on $mux $procmux$10310. dead port 2/2 on $mux $procmux$9482. dead port 2/2 on $mux $procmux$9484. dead port 2/2 on $mux $procmux$9486. dead port 2/2 on $mux $procmux$1247. dead port 2/2 on $mux $procmux$9494. dead port 2/2 on $mux $procmux$10147. dead port 2/2 on $mux $procmux$9496. dead port 2/2 on $mux $procmux$3657. dead port 2/2 on $mux $procmux$9498. dead port 2/2 on $mux $procmux$10312. dead port 2/2 on $mux $procmux$9506. dead port 2/2 on $mux $procmux$3659. dead port 2/2 on $mux $procmux$9508. dead port 2/2 on $mux $procmux$1322. dead port 2/2 on $mux $procmux$9510. dead port 2/2 on $mux $procmux$3661. dead port 2/2 on $mux $procmux$9518. dead port 2/2 on $mux $procmux$9520. dead port 2/2 on $mux $procmux$14662. dead port 2/2 on $mux $procmux$9522. dead port 1/2 on $mux $procmux$5635. dead port 2/2 on $mux $procmux$9530. dead port 2/2 on $mux $procmux$5637. dead port 2/2 on $mux $procmux$9532. dead port 2/2 on $mux $procmux$10504. dead port 2/2 on $mux $procmux$9534. dead port 2/2 on $mux $procmux$5639. dead port 2/2 on $mux $procmux$9542. dead port 2/2 on $mux $procmux$14664. dead port 2/2 on $mux $procmux$9544. dead port 2/2 on $mux $procmux$5641. dead port 2/2 on $mux $procmux$9546. dead port 2/2 on $mux $procmux$9554. dead port 2/2 on $mux $procmux$11883. dead port 2/2 on $mux $procmux$9556. dead port 2/2 on $mux $procmux$9558. dead port 2/2 on $mux $procmux$11046. dead port 2/2 on $mux $procmux$9566. dead port 2/2 on $mux $procmux$11885. dead port 2/2 on $mux $procmux$9568. dead port 2/2 on $mux $procmux$9570. dead port 2/2 on $mux $procmux$11887. dead port 2/2 on $mux $procmux$9578. dead port 2/2 on $mux $procmux$13226. dead port 2/2 on $mux $procmux$9580. dead port 2/2 on $mux $procmux$12478. dead port 2/2 on $mux $procmux$9582. dead port 2/2 on $mux $procmux$13228. dead port 2/2 on $mux $procmux$9590. dead port 2/2 on $mux $procmux$9592. dead port 2/2 on $mux $procmux$11048. dead port 2/2 on $mux $procmux$9594. dead port 2/2 on $mux $procmux$9602. dead port 2/2 on $mux $procmux$13230. dead port 2/2 on $mux $procmux$9604. dead port 2/2 on $mux $procmux$3685. dead port 2/2 on $mux $procmux$9606. dead port 2/2 on $mux $procmux$9614. dead port 2/2 on $mux $procmux$3687. dead port 2/2 on $mux $procmux$9616. dead port 1/2 on $mux $procmux$5669. dead port 2/2 on $mux $procmux$9618. dead port 2/2 on $mux $procmux$5671. dead port 2/2 on $mux $procmux$9626. dead port 2/2 on $mux $procmux$9628. dead port 2/2 on $mux $procmux$5673. dead port 2/2 on $mux $procmux$9630. dead port 2/2 on $mux $procmux$3689. dead port 2/2 on $mux $procmux$9638. dead port 2/2 on $mux $procmux$5675. dead port 2/2 on $mux $procmux$9640. dead port 2/2 on $mux $procmux$9642. dead port 2/2 on $mux $procmux$9650. dead port 2/2 on $mux $procmux$12480. dead port 2/2 on $mux $procmux$9652. dead port 2/2 on $mux $procmux$1324. dead port 2/2 on $mux $procmux$9654. dead port 2/2 on $mux $procmux$12482. dead port 2/2 on $mux $procmux$10506. dead port 2/2 on $mux $procmux$1249. dead port 2/2 on $mux $procmux$14687. dead port 2/2 on $mux $procmux$14689. dead port 2/2 on $mux $procmux$11050. dead port 2/2 on $mux $procmux$10508. dead port 1/2 on $mux $procmux$5703. dead port 2/2 on $mux $procmux$5705. dead port 2/2 on $mux $procmux$9821. dead port 2/2 on $mux $procmux$5707. dead port 2/2 on $mux $procmux$9823. dead port 2/2 on $mux $procmux$3713. dead port 2/2 on $mux $procmux$9825. dead port 2/2 on $mux $procmux$5709. dead port 1/2 on $mux $procmux$1965. dead port 2/2 on $mux $procmux$3715. dead port 2/2 on $mux $procmux$1967. dead port 2/2 on $mux $procmux$3717. dead port 2/2 on $mux $procmux$10149. dead port 2/2 on $mux $procmux$1969. dead port 2/2 on $mux $procmux$11429. dead port 2/2 on $mux $procmux$1971. dead port 2/2 on $mux $procmux$11431. dead port 2/2 on $mux $procmux$9848. dead port 2/2 on $mux $procmux$9850. dead port 2/2 on $mux $procmux$13259. dead port 2/2 on $mux $procmux$9852. dead port 1/2 on $mux $procmux$5737. dead port 2/2 on $mux $procmux$5739. dead port 2/2 on $mux $procmux$11433. dead port 2/2 on $mux $procmux$5741. dead port 2/2 on $mux $procmux$13261. dead port 2/2 on $mux $procmux$5743. dead port 2/2 on $mux $procmux$13263. dead port 2/2 on $mux $procmux$3741. dead port 2/2 on $mux $procmux$3743. dead port 2/2 on $mux $procmux$3745. dead port 2/2 on $mux $procmux$9875. dead port 2/2 on $mux $procmux$14712. dead port 2/2 on $mux $procmux$9877. dead port 2/2 on $mux $procmux$9879. dead port 2/2 on $mux $procmux$14714. dead port 1/2 on $mux $procmux$1994. dead port 2/2 on $mux $procmux$1996. dead port 2/2 on $mux $procmux$12510. dead port 2/2 on $mux $procmux$1998. dead port 1/2 on $mux $procmux$5771. dead port 2/2 on $mux $procmux$5773. dead port 2/2 on $mux $procmux$5775. dead port 2/2 on $mux $procmux$2000. dead port 2/2 on $mux $procmux$5777. dead port 2/2 on $mux $procmux$9902. dead port 2/2 on $mux $procmux$12512. dead port 2/2 on $mux $procmux$9904. dead port 2/2 on $mux $procmux$11914. dead port 2/2 on $mux $procmux$9906. dead port 2/2 on $mux $procmux$12514. dead port 2/2 on $mux $procmux$3769. dead port 2/2 on $mux $procmux$3771. dead port 2/2 on $mux $procmux$3773. dead port 2/2 on $mux $procmux$11916. dead port 2/2 on $mux $procmux$11918. dead port 1/2 on $mux $procmux$5805. dead port 2/2 on $mux $procmux$5807. dead port 2/2 on $mux $procmux$5809. dead port 2/2 on $mux $procmux$5811. dead port 2/2 on $mux $procmux$9929. dead port 2/2 on $mux $procmux$9931. dead port 2/2 on $mux $procmux$9933. dead port 2/2 on $mux $procmux$13292. dead port 1/2 on $mux $procmux$2023. dead port 2/2 on $mux $procmux$2025. dead port 2/2 on $mux $procmux$13294. dead port 2/2 on $mux $procmux$2027. dead port 2/2 on $mux $procmux$14737. dead port 2/2 on $mux $procmux$2029. dead port 2/2 on $mux $procmux$3797. dead port 2/2 on $mux $procmux$14739. dead port 2/2 on $mux $procmux$3799. dead port 2/2 on $mux $procmux$13296. dead port 2/2 on $mux $procmux$3801. dead port 1/2 on $mux $procmux$5839. dead port 2/2 on $mux $procmux$9956. dead port 2/2 on $mux $procmux$5841. dead port 2/2 on $mux $procmux$9958. dead port 2/2 on $mux $procmux$9960. dead port 2/2 on $mux $procmux$5843. dead port 2/2 on $mux $procmux$5845. dead port 2/2 on $mux $procmux$1145. dead port 2/2 on $mux $procmux$10064. dead port 2/2 on $mux $procmux$11075. dead port 2/2 on $mux $procmux$10066. dead port 2/2 on $mux $procmux$11077. dead port 2/2 on $mux $procmux$12542. dead port 2/2 on $mux $procmux$11079. dead port 2/2 on $mux $procmux$9983. dead port 1/2 on $mux $procmux$2052. dead port 2/2 on $mux $procmux$9985. dead port 2/2 on $mux $procmux$2054. dead port 2/2 on $mux $procmux$9987. dead port 2/2 on $mux $procmux$12544. dead port 2/2 on $mux $procmux$3825. dead port 1/2 on $mux $procmux$5873. dead port 2/2 on $mux $procmux$5875. dead port 2/2 on $mux $procmux$2056. dead port 2/2 on $mux $procmux$5877. Removed 1312 multiplexer ports. 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. New ctrl vector for $pmux cell $procmux$1303: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16528 } New ctrl vector for $pmux cell $procmux$8934: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16530 } New ctrl vector for $pmux cell $procmux$1687: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16532 } New ctrl vector for $pmux cell $procmux$14902: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16534 } New ctrl vector for $pmux cell $procmux$14772: { $auto$opt_reduce.cc:134:opt_pmux$16536 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$2180: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16538 } New ctrl vector for $pmux cell $procmux$14850: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16540 } New ctrl vector for $pmux cell $procmux$4656: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16542 } New ctrl vector for $pmux cell $procmux$5174: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16544 } New ctrl vector for $pmux cell $procmux$11502: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16546 } New ctrl vector for $pmux cell $procmux$2711: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16548 } New ctrl vector for $pmux cell $procmux$12879: { $auto$opt_reduce.cc:134:opt_pmux$16550 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$13044: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16552 } New ctrl vector for $pmux cell $procmux$8963: { $auto$opt_reduce.cc:134:opt_pmux$16554 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$4416: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16556 } New ctrl vector for $pmux cell $procmux$1153: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16558 } New ctrl vector for $pmux cell $procmux$10459: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16560 } New ctrl vector for $pmux cell $procmux$12333: { $auto$opt_reduce.cc:134:opt_pmux$16562 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$14824: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16564 } New ctrl vector for $pmux cell $procmux$10913: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16566 } New ctrl vector for $pmux cell $procmux$6444: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16568 } New ctrl vector for $pmux cell $procmux$4212: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16570 } New ctrl vector for $pmux cell $procmux$8992: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16572 } New ctrl vector for $pmux cell $procmux$5205: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16574 } New ctrl vector for $pmux cell $procmux$12207: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16576 } New ctrl vector for $pmux cell $procmux$11773: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16578 } New ctrl vector for $pmux cell $procmux$6758: $auto$opt_reduce.cc:134:opt_pmux$16580 New ctrl vector for $pmux cell $procmux$4686: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16582 } New ctrl vector for $pmux cell $procmux$10347: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16584 } New ctrl vector for $pmux cell $procmux$13400: { $auto$opt_reduce.cc:134:opt_pmux$16586 $procmux$13401_CMP } New ctrl vector for $pmux cell $procmux$2531: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16588 } New ctrl vector for $pmux cell $procmux$14980: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16590 } New ctrl vector for $pmux cell $procmux$7693: { $procmux$12864_CMP $procmux$13401_CMP $auto$opt_reduce.cc:134:opt_pmux$16592 } New ctrl vector for $pmux cell $procmux$9021: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16594 } New ctrl vector for $pmux cell $procmux$11532: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16596 } New ctrl vector for $pmux cell $procmux$14495: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16598 } New ctrl vector for $pmux cell $procmux$2741: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16600 } New ctrl vector for $pmux cell $procmux$5236: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16602 } New ctrl vector for $pmux cell $procmux$10101: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16604 } New ctrl vector for $pmux cell $procmux$8429: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16606 } New ctrl vector for $pmux cell $procmux$1713: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16608 } New ctrl vector for $pmux cell $procmux$12621: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16610 } New ctrl vector for $pmux cell $procmux$3388: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16612 } New ctrl vector for $pmux cell $procmux$6269: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16614 } New ctrl vector for $pmux cell $procmux$10971: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16616 } New ctrl vector for $pmux cell $procmux$6129: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16618 } New ctrl vector for $pmux cell $procmux$4096: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16620 } New ctrl vector for $pmux cell $procmux$9050: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16622 } New ctrl vector for $pmux cell $procmux$1178: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16624 } New ctrl vector for $pmux cell $procmux$2267: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16626 } New ctrl vector for $pmux cell $procmux$1028: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16628 } New ctrl vector for $pmux cell $procmux$5267: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16630 } New ctrl vector for $pmux cell $procmux$4716: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16632 } New ctrl vector for $pmux cell $procmux$1203: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16634 } New ctrl vector for $pmux cell $procmux$10128: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16636 } New ctrl vector for $pmux cell $procmux$11682: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16638 } New ctrl vector for $pmux cell $procmux$13077: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16640 } New ctrl vector for $pmux cell $procmux$15110: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16642 } New ctrl vector for $pmux cell $procmux$9079: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16644 } New ctrl vector for $pmux cell $procmux$10074: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16646 } New ctrl vector for $pmux cell $procmux$11116: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16648 } New ctrl vector for $pmux cell $procmux$6479: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16650 } New ctrl vector for $pmux cell $procmux$3416: { $auto$opt_reduce.cc:134:opt_pmux$16652 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$12717: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16654 } New ctrl vector for $pmux cell $procmux$8457: { $auto$opt_reduce.cc:134:opt_pmux$16656 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$11087: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16658 } New ctrl vector for $pmux cell $procmux$5298: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16660 } New ctrl vector for $pmux cell $procmux$1739: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16662 } New ctrl vector for $pmux cell $procmux$14520: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16664 } New ctrl vector for $pmux cell $procmux$2771: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16666 } New ctrl vector for $pmux cell $procmux$4446: { $auto$opt_reduce.cc:134:opt_pmux$16668 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$4241: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16670 } New ctrl vector for $pmux cell $procmux$11203: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16672 } New ctrl vector for $pmux cell $procmux$14345: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16674 } New ctrl vector for $pmux cell $procmux$9108: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16676 } New ctrl vector for $pmux cell $procmux$2093: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16678 } New ctrl vector for $pmux cell $procmux$4746: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16680 } New ctrl vector for $pmux cell $procmux$10291: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16682 } New ctrl vector for $pmux cell $procmux$12365: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16684 } New ctrl vector for $pmux cell $procmux$10797: { $auto$opt_reduce.cc:134:opt_pmux$16686 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$2383: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16688 } New ctrl vector for $pmux cell $procmux$13341: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16690 } New ctrl vector for $pmux cell $procmux$10209: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16692 } New ctrl vector for $pmux cell $procmux$8485: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16694 } New ctrl vector for $pmux cell $procmux$4009: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16696 } New ctrl vector for $pmux cell $procmux$11622: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16698 } New ctrl vector for $pmux cell $procmux$5329: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16700 } New ctrl vector for $pmux cell $procmux$11262: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16702 } New ctrl vector for $pmux cell $procmux$3444: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16704 } New ctrl vector for $pmux cell $procmux$12912: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16706 } New ctrl vector for $pmux cell $procmux$9137: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16708 } New ctrl vector for $pmux cell $procmux$11804: { $auto$opt_reduce.cc:134:opt_pmux$16710 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$10826: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16712 } New ctrl vector for $pmux cell $procmux$10182: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16714 } New ctrl vector for $pmux cell $procmux$1765: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16716 } New ctrl vector for $pmux cell $procmux$11352: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16718 } New ctrl vector for $pmux cell $procmux$10431: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16720 } New ctrl vector for $pmux cell $procmux$14545: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16722 } New ctrl vector for $pmux cell $procmux$12145: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16724 } New ctrl vector for $pmux cell $procmux$1353: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16726 } New ctrl vector for $pmux cell $procmux$11472: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16728 } New ctrl vector for $pmux cell $procmux$5924: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16730 } New ctrl vector for $pmux cell $procmux$5890: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16732 } New ctrl vector for $pmux cell $procmux$14928: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16734 } New ctrl vector for $pmux cell $procmux$4776: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16736 } New ctrl vector for $pmux cell $procmux$9166: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16738 } New ctrl vector for $pmux cell $procmux$6304: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16740 } New ctrl vector for $pmux cell $procmux$2801: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16742 } New ctrl vector for $pmux cell $procmux$5360: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16744 } New ctrl vector for $pmux cell $procmux$2151: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16746 } New ctrl vector for $pmux cell $procmux$8513: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16748 } New ctrl vector for $pmux cell $procmux$6514: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16750 } New ctrl vector for $pmux cell $procmux$15006: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16752 } New ctrl vector for $pmux cell $procmux$3472: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16754 } New ctrl vector for $pmux cell $procmux$1531: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16756 } New ctrl vector for $pmux cell $procmux$13110: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16758 } New ctrl vector for $pmux cell $procmux$12238: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16760 } New ctrl vector for $pmux cell $procmux$10655: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16762 } New ctrl vector for $pmux cell $procmux$12083: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16764 } New ctrl vector for $pmux cell $procmux$5992: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16766 } New ctrl vector for $pmux cell $procmux$9195: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16768 } New ctrl vector for $pmux cell $procmux$14370: { $auto$opt_reduce.cc:134:opt_pmux$16770 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$2561: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16772 } New ctrl vector for $pmux cell $procmux$1791: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16774 } New ctrl vector for $pmux cell $procmux$10543: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16776 } New ctrl vector for $pmux cell $procmux$5391: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16778 } New ctrl vector for $pmux cell $procmux$11000: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16780 } New ctrl vector for $pmux cell $procmux$4125: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16782 } New ctrl vector for $pmux cell $procmux$4270: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16784 } New ctrl vector for $pmux cell $procmux$8541: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16786 } New ctrl vector for $pmux cell $procmux$12397: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16788 } New ctrl vector for $pmux cell $procmux$2209: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16790 } New ctrl vector for $pmux cell $procmux$3500: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16792 } New ctrl vector for $pmux cell $procmux$4806: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16794 } New ctrl vector for $pmux cell $procmux$6164: { $auto$opt_reduce.cc:134:opt_pmux$16796 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$9224: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16798 } New ctrl vector for $pmux cell $procmux$14570: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16800 } New ctrl vector for $pmux cell $procmux$10711: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16802 } New ctrl vector for $pmux cell $procmux$2831: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16804 } New ctrl vector for $pmux cell $procmux$2296: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16806 } New ctrl vector for $pmux cell $procmux$2122: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16808 } New ctrl vector for $pmux cell $procmux$5422: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16810 } New ctrl vector for $pmux cell $procmux$1557: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16812 } New ctrl vector for $pmux cell $procmux$4476: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16814 } New ctrl vector for $pmux cell $procmux$10403: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16816 } New ctrl vector for $pmux cell $procmux$8569: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16818 } New ctrl vector for $pmux cell $procmux$14876: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16820 } New ctrl vector for $pmux cell $procmux$1817: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16822 } New ctrl vector for $pmux cell $procmux$9253: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16824 } New ctrl vector for $pmux cell $procmux$6549: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16826 } New ctrl vector for $pmux cell $procmux$4836: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16828 } New ctrl vector for $pmux cell $procmux$3528: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16830 } New ctrl vector for $pmux cell $procmux$3951: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16832 } New ctrl vector for $pmux cell $procmux$13143: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16834 } New ctrl vector for $pmux cell $procmux$11835: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16836 } New ctrl vector for $pmux cell $procmux$12945: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16838 } New ctrl vector for $pmux cell $procmux$10487: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16840 } New ctrl vector for $pmux cell $procmux$11174: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16842 } New ctrl vector for $pmux cell $procmux$11712: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16844 } New ctrl vector for $pmux cell $procmux$6339: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16846 } New ctrl vector for $pmux cell $procmux$15136: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16848 } New ctrl vector for $pmux cell $procmux$9282: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16850 } New ctrl vector for $pmux cell $procmux$11145: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16852 } New ctrl vector for $pmux cell $procmux$14595: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16854 } New ctrl vector for $pmux cell $procmux$2861: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16856 } New ctrl vector for $pmux cell $procmux$11382: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16858 } New ctrl vector for $pmux cell $procmux$8597: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16860 } New ctrl vector for $pmux cell $procmux$10884: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16862 } New ctrl vector for $pmux cell $procmux$14395: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16864 } New ctrl vector for $pmux cell $procmux$3556: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16866 } New ctrl vector for $pmux cell $procmux$12557: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16868 } New ctrl vector for $pmux cell $procmux$12052: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16870 } New ctrl vector for $pmux cell $procmux$4299: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16872 } New ctrl vector for $pmux cell $procmux$10855: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16874 } New ctrl vector for $pmux cell $procmux$9311: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16876 } New ctrl vector for $pmux cell $procmux$1843: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16878 } New ctrl vector for $pmux cell $procmux$4866: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16880 } New ctrl vector for $pmux cell $procmux$4038: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16882 } New ctrl vector for $pmux cell $procmux$15032: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16884 } New ctrl vector for $pmux cell $procmux$12429: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16886 } New ctrl vector for $pmux cell $procmux$10047: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16888 } New ctrl vector for $pmux cell $procmux$5958: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16890 } New ctrl vector for $pmux cell $procmux$1583: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16892 } New ctrl vector for $pmux cell $procmux$1128: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16894 } New ctrl vector for $pmux cell $procmux$12589: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16896 } New ctrl vector for $pmux cell $procmux$4154: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16898 } New ctrl vector for $pmux cell $procmux$8625: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16900 } New ctrl vector for $pmux cell $procmux$12685: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16902 } New ctrl vector for $pmux cell $procmux$9340: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16904 } New ctrl vector for $pmux cell $procmux$13176: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16906 } New ctrl vector for $pmux cell $procmux$5516: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16908 } New ctrl vector for $pmux cell $procmux$6584: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16910 } New ctrl vector for $pmux cell $procmux$10571: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$16912 } New ctrl vector for $pmux cell $procmux$3584: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16914 } New ctrl vector for $pmux cell $procmux$4506: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16916 } New ctrl vector for $pmux cell $procmux$14620: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16918 } New ctrl vector for $pmux cell $procmux$1869: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16920 } New ctrl vector for $pmux cell $procmux$11029: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16922 } New ctrl vector for $pmux cell $procmux$2891: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16924 } New ctrl vector for $pmux cell $procmux$1103: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16926 } New ctrl vector for $pmux cell $procmux$2591: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16928 } New ctrl vector for $pmux cell $procmux$9369: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16930 } New ctrl vector for $pmux cell $procmux$11292: { $auto$opt_reduce.cc:134:opt_pmux$16932 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$11866: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16934 } New ctrl vector for $pmux cell $procmux$5550: { $auto$opt_reduce.cc:134:opt_pmux$16936 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$10627: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16938 } New ctrl vector for $pmux cell $procmux$8653: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16940 } New ctrl vector for $pmux cell $procmux$10942: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16942 } New ctrl vector for $pmux cell $procmux$3612: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16944 } New ctrl vector for $pmux cell $procmux$1479: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$16946 } New ctrl vector for $pmux cell $procmux$11959: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$16948 } New ctrl vector for $pmux cell $procmux$1609: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16950 } New ctrl vector for $pmux cell $procmux$6199: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16952 } New ctrl vector for $pmux cell $procmux$11990: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16954 } New ctrl vector for $pmux cell $procmux$6374: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$16956 } New ctrl vector for $pmux cell $procmux$3922: { $auto$opt_reduce.cc:134:opt_pmux$16958 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$15159: { $auto$opt_reduce.cc:134:opt_pmux$16960 $procmux$10013_CMP $procmux$1048_CMP } New ctrl vector for $pmux cell $procmux$4328: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16962 } New ctrl vector for $pmux cell $procmux$1053: { $auto$opt_reduce.cc:134:opt_pmux$16964 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$5584: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$16966 } New ctrl vector for $pmux cell $procmux$12749: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16968 } New ctrl vector for $pmux cell $procmux$14645: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$16970 } New ctrl vector for $pmux cell $procmux$8681: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16972 } New ctrl vector for $pmux cell $procmux$12461: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16974 } New ctrl vector for $pmux cell $procmux$12978: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16976 } New ctrl vector for $pmux cell $procmux$2921: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$16978 } New ctrl vector for $pmux cell $procmux$14420: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16980 } New ctrl vector for $pmux cell $procmux$3640: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$16982 } New ctrl vector for $pmux cell $procmux$13209: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$16984 } New ctrl vector for $pmux cell $procmux$1228: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$16986 } New ctrl vector for $pmux cell $procmux$11412: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$16988 } New ctrl vector for $pmux cell $procmux$9455: $auto$opt_reduce.cc:134:opt_pmux$16990 New ctrl vector for $pmux cell $procmux$5618: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$16992 } New ctrl vector for $pmux cell $procmux$4536: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$16994 } New ctrl vector for $pmux cell $procmux$6619: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$16996 } New ctrl vector for $pmux cell $procmux$2325: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$16998 } New ctrl vector for $pmux cell $procmux$11592: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$17000 } New ctrl vector for $pmux cell $procmux$8709: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$17002 } New ctrl vector for $pmux cell $procmux$14954: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$17004 } New ctrl vector for $pmux cell $procmux$4957: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17006 } New ctrl vector for $pmux cell $procmux$14798: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$17008 } New ctrl vector for $pmux cell $procmux$2621: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$17010 } New ctrl vector for $pmux cell $procmux$1505: { $auto$opt_reduce.cc:134:opt_pmux$17012 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$12021: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$17014 } New ctrl vector for $pmux cell $procmux$3668: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$17016 } New ctrl vector for $pmux cell $procmux$15058: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$17018 } New ctrl vector for $pmux cell $procmux$8737: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$17020 } New ctrl vector for $pmux cell $procmux$12846: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17022 } New ctrl vector for $pmux cell $procmux$5652: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$17024 } New ctrl vector for $pmux cell $procmux$4988: { $auto$opt_reduce.cc:134:opt_pmux$17026 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$14670: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$17028 } New ctrl vector for $pmux cell $procmux$1635: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17030 } New ctrl vector for $pmux cell $procmux$10319: { $auto$opt_reduce.cc:134:opt_pmux$17032 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$12176: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$17034 } New ctrl vector for $pmux cell $procmux$2238: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$17036 } New ctrl vector for $pmux cell $procmux$8765: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$17038 } New ctrl vector for $pmux cell $procmux$12301: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17040 } New ctrl vector for $pmux cell $procmux$4566: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$17042 } New ctrl vector for $pmux cell $procmux$5019: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$17044 } New ctrl vector for $pmux cell $procmux$1948: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17046 } New ctrl vector for $pmux cell $procmux$4183: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$17048 } New ctrl vector for $pmux cell $procmux$14445: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$17050 } New ctrl vector for $pmux cell $procmux$6654: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$17052 } New ctrl vector for $pmux cell $procmux$5686: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$17054 } New ctrl vector for $pmux cell $procmux$8793: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$17056 } New ctrl vector for $pmux cell $procmux$3696: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$17058 } New ctrl vector for $pmux cell $procmux$2471: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17060 } New ctrl vector for $pmux cell $procmux$13011: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$17062 } New ctrl vector for $pmux cell $procmux$9804: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17064 } New ctrl vector for $pmux cell $procmux$13242: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$17066 } New ctrl vector for $pmux cell $procmux$11897: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$17068 } New ctrl vector for $pmux cell $procmux$12493: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17070 } New ctrl vector for $pmux cell $procmux$14695: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$17072 } New ctrl vector for $pmux cell $procmux$11058: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$17074 } New ctrl vector for $pmux cell $procmux$10599: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$17076 } New ctrl vector for $pmux cell $procmux$10515: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$17078 } New ctrl vector for $pmux cell $procmux$3010: $auto$opt_reduce.cc:134:opt_pmux$17080 New ctrl vector for $pmux cell $procmux$3893: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17082 } New ctrl vector for $pmux cell $procmux$5050: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$17084 } New ctrl vector for $pmux cell $procmux$9831: { $auto$opt_reduce.cc:134:opt_pmux$17086 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$2651: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17088 } New ctrl vector for $pmux cell $procmux$5720: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17090 } New ctrl vector for $pmux cell $procmux$1378: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$17092 } New ctrl vector for $pmux cell $procmux$8821: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$17094 } New ctrl vector for $pmux cell $procmux$12114: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$17096 } New ctrl vector for $pmux cell $procmux$3724: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$17098 } New ctrl vector for $pmux cell $procmux$11652: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$17100 } New ctrl vector for $pmux cell $procmux$10020: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$17102 } New ctrl vector for $pmux cell $procmux$1977: { $auto$opt_reduce.cc:134:opt_pmux$17104 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$10155: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$17106 } New ctrl vector for $pmux cell $procmux$6026: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$17108 } New ctrl vector for $pmux cell $procmux$9858: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$17110 } New ctrl vector for $pmux cell $procmux$1661: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$17112 } New ctrl vector for $pmux cell $procmux$4596: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17114 } New ctrl vector for $pmux cell $procmux$5754: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$17116 } New ctrl vector for $pmux cell $procmux$13275: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$17118 } New ctrl vector for $pmux cell $procmux$11442: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17120 } New ctrl vector for $pmux cell $procmux$4067: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17122 } New ctrl vector for $pmux cell $procmux$3752: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$17124 } New ctrl vector for $pmux cell $procmux$6409: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$17126 } New ctrl vector for $pmux cell $procmux$8849: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$17128 } New ctrl vector for $pmux cell $procmux$1078: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$17130 } New ctrl vector for $pmux cell $procmux$9885: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$17132 } New ctrl vector for $pmux cell $procmux$5081: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$17134 } New ctrl vector for $pmux cell $procmux$10683: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$17136 } New ctrl vector for $pmux cell $procmux$5788: { $procmux$10001_CMP $auto$opt_reduce.cc:134:opt_pmux$17138 } New ctrl vector for $pmux cell $procmux$2006: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$17140 } New ctrl vector for $pmux cell $procmux$14720: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$17142 } New ctrl vector for $pmux cell $procmux$1328: { $procmux$10005_CMP $auto$opt_reduce.cc:134:opt_pmux$17144 } New ctrl vector for $pmux cell $procmux$9912: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$17146 } New ctrl vector for $pmux cell $procmux$3980: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$17148 } New ctrl vector for $pmux cell $procmux$12525: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$17150 } New ctrl vector for $pmux cell $procmux$11562: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$17152 } New ctrl vector for $pmux cell $procmux$3780: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$17154 } New ctrl vector for $pmux cell $procmux$2681: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$17156 } New ctrl vector for $pmux cell $procmux$6234: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$17158 } New ctrl vector for $pmux cell $procmux$1253: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$17160 } New ctrl vector for $pmux cell $procmux$5822: { $procmux$10002_CMP $auto$opt_reduce.cc:134:opt_pmux$17162 } New ctrl vector for $pmux cell $procmux$11322: { $procmux$10022_CMP $auto$opt_reduce.cc:134:opt_pmux$17164 } New ctrl vector for $pmux cell $procmux$11928: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$17166 } New ctrl vector for $pmux cell $procmux$4626: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$17168 } New ctrl vector for $pmux cell $procmux$9939: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$17170 } New ctrl vector for $pmux cell $procmux$5112: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$17172 } New ctrl vector for $pmux cell $procmux$10768: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17174 } New ctrl vector for $pmux cell $procmux$2064: { $procmux$10024_CMP $auto$opt_reduce.cc:134:opt_pmux$17176 } New ctrl vector for $pmux cell $procmux$2035: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$17178 } New ctrl vector for $pmux cell $procmux$14470: { $procmux$10025_CMP $auto$opt_reduce.cc:134:opt_pmux$17180 } New ctrl vector for $pmux cell $procmux$2501: { $auto$opt_reduce.cc:134:opt_pmux$17182 $procmux$10021_CMP } New ctrl vector for $pmux cell $procmux$10375: { $procmux$10023_CMP $auto$opt_reduce.cc:134:opt_pmux$17184 } New ctrl vector for $pmux cell $procmux$3808: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$17186 } New ctrl vector for $pmux cell $procmux$9966: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17188 } New ctrl vector for $pmux cell $procmux$5856: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$17190 } New ctrl vector for $pmux cell $procmux$14746: { $procmux$10009_CMP $auto$opt_reduce.cc:134:opt_pmux$17192 } New ctrl vector for $pmux cell $procmux$13308: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$17194 } New ctrl vector for $pmux cell $procmux$15084: { $procmux$10006_CMP $auto$opt_reduce.cc:134:opt_pmux$17196 } New ctrl vector for $pmux cell $procmux$12653: { $procmux$10004_CMP $auto$opt_reduce.cc:134:opt_pmux$17198 } New ctrl vector for $pmux cell $procmux$2354: { $procmux$10007_CMP $auto$opt_reduce.cc:134:opt_pmux$17200 } New ctrl vector for $pmux cell $procmux$1278: { $procmux$10003_CMP $auto$opt_reduce.cc:134:opt_pmux$17202 } New ctrl vector for $pmux cell $procmux$5143: { $procmux$10026_CMP $auto$opt_reduce.cc:134:opt_pmux$17204 } New ctrl vector for $pmux cell $procmux$9993: { $procmux$10000_CMP $auto$opt_reduce.cc:134:opt_pmux$17206 } New ctrl vector for $pmux cell $procmux$1403: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$17208 } New ctrl vector for $pmux cell $procmux$12781: { $procmux$10008_CMP $auto$opt_reduce.cc:134:opt_pmux$17210 } Optimizing cells in module \rv30. Performed a total of 343 changes. 2.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 373 cells. 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 1 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 2 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 3 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 4 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 5 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 6 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 7 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 8 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 9 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 10 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 11 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 12 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 13 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 14 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 15 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 16 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 17 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 18 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 19 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 20 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 21 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 22 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 23 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 24 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 25 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 26 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 27 on $procdff$16522 ($dff) from module rv30. Setting constant 1-bit at position 28 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 29 on $procdff$16522 ($dff) from module rv30. Setting constant 0-bit at position 0 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 1 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 2 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 3 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 4 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 5 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 6 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 7 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 8 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 9 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 10 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 11 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 12 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 13 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 14 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 15 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 16 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 17 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 18 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 19 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 20 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 21 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 22 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 23 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 24 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 25 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 26 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 27 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 28 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 29 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 30 on $procdff$16524 ($dff) from module rv30. Setting constant 0-bit at position 31 on $procdff$16524 ($dff) from module rv30. Setting constant 1-bit at position 0 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 1 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 2 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 3 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 4 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 5 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 6 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 7 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 8 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 9 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 10 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 11 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 12 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 13 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 14 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 15 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 16 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 17 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 18 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 19 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 20 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 21 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 22 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 23 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 24 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 25 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 26 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 27 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 28 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 29 on $procdff$16525 ($dff) from module rv30. Setting constant 1-bit at position 30 on $procdff$16525 ($dff) from module rv30. Setting constant 0-bit at position 31 on $procdff$16525 ($dff) from module rv30. 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. Warning: Driver-driver conflict for \rvx[0] [31] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [30] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [29] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [28] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [27] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [26] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [25] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [24] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [23] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [22] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [21] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [20] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [19] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [18] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [17] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [16] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [15] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [14] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [13] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [12] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [11] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [10] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [9] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [8] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [7] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [6] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [5] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [4] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [3] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [2] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [1] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[0] [0] between cell $procdff$16400.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [31] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [30] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [29] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [28] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [27] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [26] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [25] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [24] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [23] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [22] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [21] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [20] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [19] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [18] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [17] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [16] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [15] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [14] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [13] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [12] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [11] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [10] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [9] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [8] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [7] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [6] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [5] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [4] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [3] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [2] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [1] between cell $procdff$16415.Q and constant 1'0 in rv30: Resolved using constant. Warning: Driver-driver conflict for \rvx[15] [0] between cell $procdff$16415.Q and constant 1'1 in rv30: Resolved using constant. Removed 60 unused cells and 8822 unused wires. 2.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/3 on $pmux $procmux$12238. dead port 2/3 on $pmux $procmux$12238. dead port 3/3 on $pmux $procmux$12238. dead port 1/3 on $pmux $procmux$1228. dead port 2/3 on $pmux $procmux$1228. dead port 3/3 on $pmux $procmux$1228. dead port 1/3 on $pmux $procmux$1203. dead port 2/3 on $pmux $procmux$1203. dead port 3/3 on $pmux $procmux$1203. dead port 1/3 on $pmux $procmux$11562. dead port 2/3 on $pmux $procmux$11562. dead port 3/3 on $pmux $procmux$11562. dead port 1/3 on $pmux $procmux$12021. dead port 2/3 on $pmux $procmux$12021. dead port 3/3 on $pmux $procmux$12021. dead port 1/3 on $pmux $procmux$12365. dead port 2/3 on $pmux $procmux$12365. dead port 3/3 on $pmux $procmux$12365. dead port 1/3 on $pmux $procmux$12397. dead port 2/3 on $pmux $procmux$12397. dead port 3/3 on $pmux $procmux$12397. dead port 1/3 on $pmux $procmux$12429. dead port 2/3 on $pmux $procmux$12429. dead port 3/3 on $pmux $procmux$12429. dead port 1/3 on $pmux $procmux$12461. dead port 2/3 on $pmux $procmux$12461. dead port 3/3 on $pmux $procmux$12461. dead port 1/3 on $pmux $procmux$12493. dead port 2/3 on $pmux $procmux$12493. dead port 3/3 on $pmux $procmux$12493. dead port 1/3 on $pmux $procmux$12525. dead port 2/3 on $pmux $procmux$12525. dead port 3/3 on $pmux $procmux$12525. dead port 1/3 on $pmux $procmux$1253. dead port 2/3 on $pmux $procmux$1253. dead port 3/3 on $pmux $procmux$1253. dead port 1/3 on $pmux $procmux$12557. dead port 2/3 on $pmux $procmux$12557. dead port 3/3 on $pmux $procmux$12557. dead port 1/3 on $pmux $procmux$12589. dead port 2/3 on $pmux $procmux$12589. dead port 3/3 on $pmux $procmux$12589. dead port 1/3 on $pmux $procmux$12621. dead port 2/3 on $pmux $procmux$12621. dead port 3/3 on $pmux $procmux$12621. dead port 1/3 on $pmux $procmux$12653. dead port 2/3 on $pmux $procmux$12653. dead port 3/3 on $pmux $procmux$12653. dead port 1/3 on $pmux $procmux$12685. dead port 2/3 on $pmux $procmux$12685. dead port 3/3 on $pmux $procmux$12685. dead port 1/3 on $pmux $procmux$12717. dead port 2/3 on $pmux $procmux$12717. dead port 3/3 on $pmux $procmux$12717. dead port 1/3 on $pmux $procmux$12749. dead port 2/3 on $pmux $procmux$12749. dead port 3/3 on $pmux $procmux$12749. dead port 1/3 on $pmux $procmux$1278. dead port 2/3 on $pmux $procmux$1278. dead port 3/3 on $pmux $procmux$1278. dead port 1/3 on $pmux $procmux$12781. dead port 2/3 on $pmux $procmux$12781. dead port 3/3 on $pmux $procmux$12781. dead port 1/3 on $pmux $procmux$11928. dead port 2/3 on $pmux $procmux$11928. dead port 3/3 on $pmux $procmux$11928. dead port 1/3 on $pmux $procmux$1178. dead port 2/3 on $pmux $procmux$1178. dead port 3/3 on $pmux $procmux$1178. dead port 1/3 on $pmux $procmux$10487. dead port 2/3 on $pmux $procmux$10487. dead port 3/3 on $pmux $procmux$10487. dead port 2/3 on $pmux $procmux$12912. dead port 3/3 on $pmux $procmux$12912. dead port 2/3 on $pmux $procmux$12945. dead port 3/3 on $pmux $procmux$12945. dead port 2/3 on $pmux $procmux$12978. dead port 3/3 on $pmux $procmux$12978. dead port 2/3 on $pmux $procmux$13011. dead port 3/3 on $pmux $procmux$13011. dead port 1/3 on $pmux $procmux$1303. dead port 2/3 on $pmux $procmux$1303. dead port 3/3 on $pmux $procmux$1303. dead port 1/3 on $pmux $procmux$13044. dead port 3/3 on $pmux $procmux$13044. dead port 2/3 on $pmux $procmux$13077. dead port 3/3 on $pmux $procmux$13077. dead port 2/3 on $pmux $procmux$13110. dead port 3/3 on $pmux $procmux$13110. dead port 2/3 on $pmux $procmux$13143. dead port 3/3 on $pmux $procmux$13143. dead port 2/3 on $pmux $procmux$13176. dead port 3/3 on $pmux $procmux$13176. dead port 2/3 on $pmux $procmux$13209. dead port 3/3 on $pmux $procmux$13209. dead port 2/3 on $pmux $procmux$13242. dead port 3/3 on $pmux $procmux$13242. dead port 2/3 on $pmux $procmux$13275. dead port 3/3 on $pmux $procmux$13275. dead port 1/3 on $pmux $procmux$1328. dead port 2/3 on $pmux $procmux$1328. dead port 3/3 on $pmux $procmux$1328. dead port 2/3 on $pmux $procmux$13308. dead port 3/3 on $pmux $procmux$13308. dead port 2/3 on $pmux $procmux$13341. dead port 3/3 on $pmux $procmux$13341. dead port 1/3 on $pmux $procmux$11835. dead port 2/3 on $pmux $procmux$11835. dead port 3/3 on $pmux $procmux$11835. dead port 1/3 on $pmux $procmux$11959. dead port 2/3 on $pmux $procmux$11959. dead port 3/3 on $pmux $procmux$11959. dead port 1/3 on $pmux $procmux$13400. dead port 3/3 on $pmux $procmux$13400. dead port 1/3 on $pmux $procmux$10074. dead port 2/3 on $pmux $procmux$10074. dead port 3/3 on $pmux $procmux$10074. dead port 1/9 on $pmux $procmux$13432. dead port 2/9 on $pmux $procmux$13432. dead port 3/9 on $pmux $procmux$13432. dead port 4/9 on $pmux $procmux$13432. dead port 5/9 on $pmux $procmux$13432. dead port 6/9 on $pmux $procmux$13432. dead port 7/9 on $pmux $procmux$13432. dead port 9/9 on $pmux $procmux$13432. dead port 1/9 on $pmux $procmux$13448. dead port 2/9 on $pmux $procmux$13448. dead port 3/9 on $pmux $procmux$13448. dead port 4/9 on $pmux $procmux$13448. dead port 5/9 on $pmux $procmux$13448. dead port 6/9 on $pmux $procmux$13448. dead port 7/9 on $pmux $procmux$13448. dead port 9/9 on $pmux $procmux$13448. dead port 1/9 on $pmux $procmux$13464. dead port 2/9 on $pmux $procmux$13464. dead port 3/9 on $pmux $procmux$13464. dead port 4/9 on $pmux $procmux$13464. dead port 5/9 on $pmux $procmux$13464. dead port 6/9 on $pmux $procmux$13464. dead port 7/9 on $pmux $procmux$13464. dead port 9/9 on $pmux $procmux$13464. dead port 1/9 on $pmux $procmux$13480. dead port 2/9 on $pmux $procmux$13480. dead port 3/9 on $pmux $procmux$13480. dead port 4/9 on $pmux $procmux$13480. dead port 5/9 on $pmux $procmux$13480. dead port 6/9 on $pmux $procmux$13480. dead port 7/9 on $pmux $procmux$13480. dead port 9/9 on $pmux $procmux$13480. dead port 1/9 on $pmux $procmux$13496. dead port 2/9 on $pmux $procmux$13496. dead port 3/9 on $pmux $procmux$13496. dead port 4/9 on $pmux $procmux$13496. dead port 5/9 on $pmux $procmux$13496. dead port 6/9 on $pmux $procmux$13496. dead port 7/9 on $pmux $procmux$13496. dead port 9/9 on $pmux $procmux$13496. dead port 1/9 on $pmux $procmux$13512. dead port 2/9 on $pmux $procmux$13512. dead port 3/9 on $pmux $procmux$13512. dead port 4/9 on $pmux $procmux$13512. dead port 5/9 on $pmux $procmux$13512. dead port 6/9 on $pmux $procmux$13512. dead port 7/9 on $pmux $procmux$13512. dead port 9/9 on $pmux $procmux$13512. dead port 1/9 on $pmux $procmux$13528. dead port 2/9 on $pmux $procmux$13528. dead port 3/9 on $pmux $procmux$13528. dead port 4/9 on $pmux $procmux$13528. dead port 5/9 on $pmux $procmux$13528. dead port 6/9 on $pmux $procmux$13528. dead port 7/9 on $pmux $procmux$13528. dead port 9/9 on $pmux $procmux$13528. dead port 1/3 on $pmux $procmux$1353. dead port 2/3 on $pmux $procmux$1353. dead port 3/3 on $pmux $procmux$1353. dead port 1/9 on $pmux $procmux$13544. dead port 2/9 on $pmux $procmux$13544. dead port 3/9 on $pmux $procmux$13544. dead port 4/9 on $pmux $procmux$13544. dead port 5/9 on $pmux $procmux$13544. dead port 6/9 on $pmux $procmux$13544. dead port 7/9 on $pmux $procmux$13544. dead port 9/9 on $pmux $procmux$13544. dead port 1/9 on $pmux $procmux$13560. dead port 2/9 on $pmux $procmux$13560. dead port 3/9 on $pmux $procmux$13560. dead port 4/9 on $pmux $procmux$13560. dead port 5/9 on $pmux $procmux$13560. dead port 6/9 on $pmux $procmux$13560. dead port 7/9 on $pmux $procmux$13560. dead port 9/9 on $pmux $procmux$13560. dead port 1/9 on $pmux $procmux$13576. dead port 2/9 on $pmux $procmux$13576. dead port 3/9 on $pmux $procmux$13576. dead port 4/9 on $pmux $procmux$13576. dead port 5/9 on $pmux $procmux$13576. dead port 6/9 on $pmux $procmux$13576. dead port 7/9 on $pmux $procmux$13576. dead port 9/9 on $pmux $procmux$13576. dead port 1/9 on $pmux $procmux$13592. dead port 2/9 on $pmux $procmux$13592. dead port 3/9 on $pmux $procmux$13592. dead port 4/9 on $pmux $procmux$13592. dead port 5/9 on $pmux $procmux$13592. dead port 6/9 on $pmux $procmux$13592. dead port 7/9 on $pmux $procmux$13592. dead port 9/9 on $pmux $procmux$13592. dead port 1/9 on $pmux $procmux$13608. dead port 2/9 on $pmux $procmux$13608. dead port 3/9 on $pmux $procmux$13608. dead port 4/9 on $pmux $procmux$13608. dead port 5/9 on $pmux $procmux$13608. dead port 6/9 on $pmux $procmux$13608. dead port 7/9 on $pmux $procmux$13608. dead port 9/9 on $pmux $procmux$13608. dead port 1/9 on $pmux $procmux$13624. dead port 2/9 on $pmux $procmux$13624. dead port 3/9 on $pmux $procmux$13624. dead port 4/9 on $pmux $procmux$13624. dead port 5/9 on $pmux $procmux$13624. dead port 6/9 on $pmux $procmux$13624. dead port 7/9 on $pmux $procmux$13624. dead port 9/9 on $pmux $procmux$13624. dead port 1/9 on $pmux $procmux$13640. dead port 2/9 on $pmux $procmux$13640. dead port 3/9 on $pmux $procmux$13640. dead port 4/9 on $pmux $procmux$13640. dead port 5/9 on $pmux $procmux$13640. dead port 6/9 on $pmux $procmux$13640. dead port 7/9 on $pmux $procmux$13640. dead port 9/9 on $pmux $procmux$13640. dead port 1/3 on $pmux $procmux$1378. dead port 2/3 on $pmux $procmux$1378. dead port 3/3 on $pmux $procmux$1378. dead port 1/3 on $pmux $procmux$1403. dead port 2/3 on $pmux $procmux$1403. dead port 3/3 on $pmux $procmux$1403. dead port 1/17 on $pmux $procmux$1428. dead port 2/17 on $pmux $procmux$1428. dead port 3/17 on $pmux $procmux$1428. dead port 4/17 on $pmux $procmux$1428. dead port 5/17 on $pmux $procmux$1428. dead port 6/17 on $pmux $procmux$1428. dead port 7/17 on $pmux $procmux$1428. dead port 8/17 on $pmux $procmux$1428. dead port 9/17 on $pmux $procmux$1428. dead port 10/17 on $pmux $procmux$1428. dead port 11/17 on $pmux $procmux$1428. dead port 12/17 on $pmux $procmux$1428. dead port 13/17 on $pmux $procmux$1428. dead port 14/17 on $pmux $procmux$1428. dead port 15/17 on $pmux $procmux$1428. dead port 16/17 on $pmux $procmux$1428. dead port 17/17 on $pmux $procmux$1428. dead port 1/3 on $pmux $procmux$12052. dead port 2/3 on $pmux $procmux$12052. dead port 3/3 on $pmux $procmux$12052. dead port 1/3 on $pmux $procmux$14395. dead port 2/3 on $pmux $procmux$14395. dead port 3/3 on $pmux $procmux$14395. dead port 1/3 on $pmux $procmux$14420. dead port 2/3 on $pmux $procmux$14420. dead port 3/3 on $pmux $procmux$14420. dead port 1/3 on $pmux $procmux$14445. dead port 2/3 on $pmux $procmux$14445. dead port 3/3 on $pmux $procmux$14445. dead port 1/3 on $pmux $procmux$11087. dead port 2/3 on $pmux $procmux$11087. dead port 3/3 on $pmux $procmux$11087. dead port 1/3 on $pmux $procmux$11116. dead port 2/3 on $pmux $procmux$11116. dead port 3/3 on $pmux $procmux$11116. dead port 1/3 on $pmux $procmux$14470. dead port 2/3 on $pmux $procmux$14470. dead port 3/3 on $pmux $procmux$14470. dead port 1/3 on $pmux $procmux$11145. dead port 2/3 on $pmux $procmux$11145. dead port 3/3 on $pmux $procmux$11145. dead port 1/3 on $pmux $procmux$14495. dead port 2/3 on $pmux $procmux$14495. dead port 3/3 on $pmux $procmux$14495. dead port 1/3 on $pmux $procmux$14520. dead port 2/3 on $pmux $procmux$14520. dead port 3/3 on $pmux $procmux$14520. dead port 1/3 on $pmux $procmux$14545. dead port 2/3 on $pmux $procmux$14545. dead port 3/3 on $pmux $procmux$14545. dead port 1/3 on $pmux $procmux$14570. dead port 2/3 on $pmux $procmux$14570. dead port 3/3 on $pmux $procmux$14570. dead port 1/3 on $pmux $procmux$14595. dead port 2/3 on $pmux $procmux$14595. dead port 3/3 on $pmux $procmux$14595. dead port 1/3 on $pmux $procmux$14620. dead port 2/3 on $pmux $procmux$14620. dead port 3/3 on $pmux $procmux$14620. dead port 1/3 on $pmux $procmux$14645. dead port 2/3 on $pmux $procmux$14645. dead port 3/3 on $pmux $procmux$14645. dead port 1/3 on $pmux $procmux$14670. dead port 2/3 on $pmux $procmux$14670. dead port 3/3 on $pmux $procmux$14670. dead port 1/3 on $pmux $procmux$14695. dead port 2/3 on $pmux $procmux$14695. dead port 3/3 on $pmux $procmux$14695. dead port 1/3 on $pmux $procmux$11174. dead port 2/3 on $pmux $procmux$11174. dead port 3/3 on $pmux $procmux$11174. dead port 1/3 on $pmux $procmux$14720. dead port 2/3 on $pmux $procmux$14720. dead port 3/3 on $pmux $procmux$14720. dead port 1/3 on $pmux $procmux$11203. dead port 2/3 on $pmux $procmux$11203. dead port 3/3 on $pmux $procmux$11203. dead port 1/3 on $pmux $procmux$12083. dead port 2/3 on $pmux $procmux$12083. dead port 3/3 on $pmux $procmux$12083. dead port 1/3 on $pmux $procmux$14798. dead port 2/3 on $pmux $procmux$14798. dead port 3/3 on $pmux $procmux$14798. dead port 1/3 on $pmux $procmux$14824. dead port 2/3 on $pmux $procmux$14824. dead port 3/3 on $pmux $procmux$14824. dead port 1/3 on $pmux $procmux$14850. dead port 2/3 on $pmux $procmux$14850. dead port 3/3 on $pmux $procmux$14850. dead port 1/3 on $pmux $procmux$14876. dead port 2/3 on $pmux $procmux$14876. dead port 3/3 on $pmux $procmux$14876. dead port 1/3 on $pmux $procmux$14902. dead port 2/3 on $pmux $procmux$14902. dead port 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$procmux$8653. dead port 2/3 on $pmux $procmux$8653. dead port 3/3 on $pmux $procmux$8653. dead port 1/3 on $pmux $procmux$8681. dead port 2/3 on $pmux $procmux$8681. dead port 3/3 on $pmux $procmux$8681. dead port 1/3 on $pmux $procmux$8709. dead port 2/3 on $pmux $procmux$8709. dead port 3/3 on $pmux $procmux$8709. dead port 1/3 on $pmux $procmux$8737. dead port 2/3 on $pmux $procmux$8737. dead port 3/3 on $pmux $procmux$8737. dead port 1/3 on $pmux $procmux$8765. dead port 2/3 on $pmux $procmux$8765. dead port 3/3 on $pmux $procmux$8765. dead port 1/3 on $pmux $procmux$8793. dead port 2/3 on $pmux $procmux$8793. dead port 3/3 on $pmux $procmux$8793. dead port 1/3 on $pmux $procmux$8821. dead port 2/3 on $pmux $procmux$8821. dead port 3/3 on $pmux $procmux$8821. dead port 1/3 on $pmux $procmux$8849. dead port 2/3 on $pmux $procmux$8849. dead port 3/3 on $pmux $procmux$8849. dead port 1/3 on $pmux $procmux$11322. dead port 2/3 on $pmux $procmux$11322. dead port 3/3 on $pmux $procmux$11322. dead port 1/3 on $pmux $procmux$11352. dead port 2/3 on $pmux $procmux$11352. dead port 3/3 on $pmux $procmux$11352. dead port 1/3 on $pmux $procmux$8992. dead port 2/3 on $pmux $procmux$8992. dead port 3/3 on $pmux $procmux$8992. dead port 1/3 on $pmux $procmux$9021. dead port 2/3 on $pmux $procmux$9021. dead port 3/3 on $pmux $procmux$9021. dead port 1/3 on $pmux $procmux$9050. dead port 2/3 on $pmux $procmux$9050. dead port 3/3 on $pmux $procmux$9050. dead port 1/3 on $pmux $procmux$9079. dead port 2/3 on $pmux $procmux$9079. dead port 3/3 on $pmux $procmux$9079. dead port 1/3 on $pmux $procmux$9108. dead port 2/3 on $pmux $procmux$9108. dead port 3/3 on $pmux $procmux$9108. dead port 1/3 on $pmux $procmux$9137. dead port 2/3 on $pmux $procmux$9137. dead port 3/3 on $pmux $procmux$9137. dead port 1/3 on $pmux $procmux$9166. dead port 2/3 on $pmux $procmux$9166. dead port 3/3 on $pmux $procmux$9166. dead port 1/3 on $pmux $procmux$9195. dead port 2/3 on $pmux $procmux$9195. dead port 3/3 on $pmux $procmux$9195. dead port 1/3 on $pmux $procmux$9224. dead port 2/3 on $pmux $procmux$9224. dead port 3/3 on $pmux $procmux$9224. dead port 1/3 on $pmux $procmux$9253. dead port 2/3 on $pmux $procmux$9253. dead port 3/3 on $pmux $procmux$9253. dead port 1/3 on $pmux $procmux$9282. dead port 2/3 on $pmux $procmux$9282. dead port 3/3 on $pmux $procmux$9282. dead port 1/3 on $pmux $procmux$9311. dead port 2/3 on $pmux $procmux$9311. dead port 3/3 on $pmux $procmux$9311. dead port 1/3 on $pmux $procmux$9340. dead port 2/3 on $pmux $procmux$9340. dead port 3/3 on $pmux $procmux$9340. dead port 1/3 on $pmux $procmux$9369. dead port 2/3 on $pmux $procmux$9369. dead port 3/3 on $pmux $procmux$9369. dead port 1/3 on $pmux $procmux$10047. dead port 2/3 on $pmux $procmux$10047. dead port 3/3 on $pmux $procmux$10047. dead port 1/3 on $pmux $procmux$10101. dead port 2/3 on $pmux $procmux$10101. dead port 3/3 on $pmux $procmux$10101. dead port 1/3 on $pmux $procmux$10128. dead port 2/3 on $pmux $procmux$10128. dead port 3/3 on $pmux $procmux$10128. dead port 1/3 on $pmux $procmux$10155. dead port 2/3 on $pmux $procmux$10155. dead port 3/3 on $pmux $procmux$10155. dead port 1/3 on $pmux $procmux$10209. dead port 2/3 on $pmux $procmux$10209. dead port 3/3 on $pmux $procmux$10209. dead port 1/3 on $pmux $procmux$9479. dead port 2/3 on $pmux $procmux$9479. dead port 3/3 on $pmux $procmux$9479. dead port 1/3 on $pmux $procmux$9491. dead port 2/3 on $pmux $procmux$9491. dead port 3/3 on $pmux $procmux$9491. dead port 1/3 on $pmux $procmux$9503. dead port 2/3 on $pmux $procmux$9503. dead port 3/3 on $pmux $procmux$9503. dead port 1/3 on $pmux $procmux$9515. dead port 2/3 on $pmux $procmux$9515. dead port 3/3 on $pmux $procmux$9515. dead port 1/3 on $pmux $procmux$9527. dead port 2/3 on $pmux $procmux$9527. dead port 3/3 on $pmux $procmux$9527. dead port 1/3 on $pmux $procmux$9539. dead port 2/3 on $pmux $procmux$9539. dead port 3/3 on $pmux $procmux$9539. dead port 1/3 on $pmux $procmux$9551. dead port 2/3 on $pmux $procmux$9551. dead port 3/3 on $pmux $procmux$9551. dead port 1/3 on $pmux $procmux$9563. dead port 2/3 on $pmux $procmux$9563. dead port 3/3 on $pmux $procmux$9563. dead port 1/3 on $pmux $procmux$9575. dead port 2/3 on $pmux $procmux$9575. dead port 3/3 on $pmux $procmux$9575. dead port 1/3 on $pmux $procmux$9587. dead port 2/3 on $pmux $procmux$9587. dead port 3/3 on $pmux $procmux$9587. dead port 1/3 on $pmux $procmux$9599. dead port 2/3 on $pmux $procmux$9599. dead port 3/3 on $pmux $procmux$9599. dead port 1/3 on $pmux $procmux$9611. dead port 2/3 on $pmux $procmux$9611. dead port 3/3 on $pmux $procmux$9611. dead port 1/3 on $pmux $procmux$9623. dead port 2/3 on $pmux $procmux$9623. dead port 3/3 on $pmux $procmux$9623. dead port 1/3 on $pmux $procmux$9635. dead port 2/3 on $pmux $procmux$9635. dead port 3/3 on $pmux $procmux$9635. dead port 1/3 on $pmux $procmux$9858. dead port 2/3 on $pmux $procmux$9858. dead port 3/3 on $pmux $procmux$9858. dead port 1/3 on $pmux $procmux$9885. dead port 2/3 on $pmux $procmux$9885. dead port 3/3 on $pmux $procmux$9885. dead port 1/3 on $pmux $procmux$9912. dead port 2/3 on $pmux $procmux$9912. dead port 3/3 on $pmux $procmux$9912. dead port 1/3 on $pmux $procmux$9939. dead port 2/3 on $pmux $procmux$9939. dead port 3/3 on $pmux $procmux$9939. dead port 1/3 on $pmux $procmux$9966. dead port 2/3 on $pmux $procmux$9966. dead port 3/3 on $pmux $procmux$9966. dead port 1/3 on $pmux $procmux$9993. dead port 2/3 on $pmux $procmux$9993. dead port 3/3 on $pmux $procmux$9993. dead port 1/3 on $pmux $procmux$11592. dead port 2/3 on $pmux $procmux$11592. dead port 3/3 on $pmux $procmux$11592. dead port 1/3 on $pmux $procmux$11897. dead port 2/3 on $pmux $procmux$11897. dead port 3/3 on $pmux $procmux$11897. dead port 1/3 on $pmux $procmux$10913. dead port 2/3 on $pmux $procmux$10913. dead port 3/3 on $pmux $procmux$10913. dead port 1/3 on $pmux $procmux$11382. dead port 2/3 on $pmux $procmux$11382. dead port 3/3 on $pmux $procmux$11382. dead port 1/3 on $pmux $procmux$1078. dead port 2/3 on $pmux $procmux$1078. dead port 3/3 on $pmux $procmux$1078. dead port 1/3 on $pmux $procmux$11412. dead port 2/3 on $pmux $procmux$11412. dead port 3/3 on $pmux $procmux$11412. dead port 1/3 on $pmux $procmux$10655. dead port 2/3 on $pmux $procmux$10655. dead port 3/3 on $pmux $procmux$10655. Removed 1330 multiplexer ports. 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. Optimizing cells in module \rv30. Performed a total of 13 changes. 2.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $procdff$16398 ($dff) from module rv30. Setting constant 1-bit at position 0 on $procdff$16523 ($dff) from module rv30. 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. Removed 17 unused cells and 602 unused wires. 2.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.10.16. Rerunning OPT passes. (Maybe there is more to do..) 2.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. Performed a total of 0 changes. 2.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.10.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $procdff$16397 ($dff) from module rv30. 2.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. Removed 0 unused cells and 4 unused wires. 2.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.10.23. Rerunning OPT passes. (Maybe there is more to do..) 2.10.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. Performed a total of 0 changes. 2.10.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.10.27. Executing OPT_DFF pass (perform DFF optimizations). Handling D = Q on $procdff$16410 ($dff) from module rv30 (removing D path). 2.10.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. Removed 2 unused cells and 3 unused wires. 2.10.29. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.10.30. Rerunning OPT passes. (Maybe there is more to do..) 2.10.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.10.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. Performed a total of 0 changes. 2.10.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.10.34. Executing OPT_DFF pass (perform DFF optimizations). 2.10.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. Removed 0 unused cells and 2 unused wires. 2.10.36. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.10.37. Rerunning OPT passes. (Maybe there is more to do..) 2.10.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.10.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. Performed a total of 0 changes. 2.10.40. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.10.41. Executing OPT_DFF pass (perform DFF optimizations). 2.10.42. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.10.43. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.10.44. Finished OPT passes. (There is nothing left to do.) 2.11. Executing FSM pass (extract and optimize FSM). 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. Performed a total of 0 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.12.9. Finished OPT passes. (There is nothing left to do.) 2.13. Executing WREDUCE pass (reducing word size of cells). 2.14. Executing PEEPOPT pass (run peephole optimizers). 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.16. Executing SHARE pass (SAT-based resource sharing). 2.17. Executing TECHMAP pass (map to technology primitives). 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.17.2. Continuing TECHMAP pass. No more expansions possible. 2.18. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module rv30: created 0 $alu and 0 $macc cells. 2.21. Executing OPT pass (performing simple optimizations). 2.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. Performed a total of 0 changes. 2.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.21.9. Finished OPT passes. (There is nothing left to do.) 2.22. Executing MEMORY pass. 2.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2.25. Executing TECHMAP pass (map to technology primitives). 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K_'. Successfully finished Verilog frontend. 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_SPRAM_'. Successfully finished Verilog frontend. 2.25.3. Continuing TECHMAP pass. No more expansions possible. 2.26. Executing ICE40_BRAMINIT pass. 2.27. Executing OPT pass (performing simple optimizations). 2.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.27.5. Finished fast OPT passes. 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.29. Executing OPT pass (performing simple optimizations). 2.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \rv30.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \rv30. Performed a total of 0 changes. 2.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.29.9. Finished OPT passes. (There is nothing left to do.) 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2.31. Executing TECHMAP pass (map to technology primitives). 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 2.31.3. Continuing TECHMAP pass. No more expansions possible. 2.32. Executing OPT pass (performing simple optimizations). 2.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.32.5. Finished fast OPT passes. 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2.33.1. Running ICE40 specific optimizations. 2.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.33.6. Finished OPT passes. (There is nothing left to do.) 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.35. Executing TECHMAP pass (map to technology primitives). 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.35.2. Continuing TECHMAP pass. No more expansions possible. 2.36. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2.38.1. Running ICE40 specific optimizations. 2.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module rv30. 2.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\rv30'. Removed a total of 0 cells. 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \rv30.. 2.38.6. Finished OPT passes. (There is nothing left to do.) 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. No more expansions possible. 2.40. Executing ABC pass (technology mapping using ABC). 2.40.1. Extracting gate netlist of module `\rv30' to `/input.blif'.. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 2.42. Executing TECHMAP pass (map to technology primitives). 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 2.42.2. Continuing TECHMAP pass. No more expansions possible. 2.43. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 0 with \SB_CARRY (#0) 0 with \SB_CARRY (#1) 0 Eliminating LUTs. Number of LUTs: 0 with \SB_CARRY (#0) 0 with \SB_CARRY (#1) 0 Combining LUTs. Number of LUTs: 0 with \SB_CARRY (#0) 0 with \SB_CARRY (#1) 0 Eliminated 0 LUTs. Combined 0 LUTs. 2.44. Executing TECHMAP pass (map to technology primitives). 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 2.44.2. Continuing TECHMAP pass. No more expansions possible. 2.45. Executing AUTONAME pass. 2.46. Executing HIERARCHY pass (managing design hierarchy). 2.46.1. Analyzing design hierarchy.. Top module: \rv30 2.46.2. Analyzing design hierarchy.. Top module: \rv30 Removed 0 unused modules. 2.47. Printing statistics. === rv30 === Number of wires: 11 Number of wire bits: 144 Number of public wires: 11 Number of public wire bits: 144 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 0 2.48. Executing CHECK pass (checking for obvious problems). Checking module rv30... Found and reported 0 problems. -- Writing to `rv30.json' using backend `json' -- 3. Executing JSON backend. Warnings: 130 unique messages, 130 total End of script. Logfile hash: 6ca7f96be1, CPU: user 122.28s system 4.90s, MEM: 139.86 MB peak Yosys 0.35 (git sha1 cc31c6e, aarch64-linux-musl-c++ 12.2.0 -fstack-clash-protection -O2 -march=armv8-a -ffile-prefix-map=/builddir/yosys-0.35=. -fPIC -Os) Time spent: 25% 1x proc_mux (31 sec), 17% 21x opt_expr (22 sec), ...