module sram (input wire [17:0] addr, inout wire [15:0] data, input wire oe, input wire we, input wire cs);

wire we, oe;		// output enable, write enable, chip select. (all active on low signal)
reg wer, oer;

assign we = wer;
assign oe = oer;

always @((addr or data) and !cs) begin
	if (read==1) begin
		wer=1'b1;
		oer=1'b0;
	end
	else if (read==0) begin
		wer=1'b0;
		oer=1'b1;
	end
end

endmodule