module ramtest(input wire clk, 
			input wire but, 
			output wire [1:0] led, 
			output [17:0] addr, 
			inout [15:0] data, 
			output wire write_enable, 
			output wire out_enable, 
			output wire chip_select);

reg [1:0] led_r;
assign led = led_r;

wire clk_1Hz;
reg [26:0] clk_div;
always @(posedge clk) clk_div = clk_div + 27'b1;
assign clk_1Hz = clk_div[26];

reg [17:0] taddr[7:0];
reg [15:0] tdata[7:0];
reg start=1'b0;

always @(posedge but) begin
	led_r = 2'b11;

	taddr[0] = 18'b011011100101101010;
	taddr[1] = 18'b011011000101101010;
	taddr[2] = 18'b011011100101101010;
	taddr[3] = 18'b001000100101101010;
	taddr[4] = 18'b011011111101101010;
	taddr[5] = 18'b001011100101111010;
	taddr[6] = 18'b011011100111101010;
	taddr[7] = 18'b001011000100101110;

	tdata[0] = 16'b1101001001010010;
	tdata[1] = 16'b0101001111010010;
	tdata[2] = 16'b1101001000000010;
	tdata[3] = 16'b1110001001110010;
	tdata[4] = 16'b1001111001010010;
	tdata[5] = 16'b1111111001010110;
	tdata[6] = 16'b1100001111000101;
	tdata[7] = 16'b0010100110100111;

	start = 1'b1;
end

reg [7:0] testaddr_r;
reg [7:0] testdata_r;
reg testoe_r;
reg testwe_r;
reg testselect_r=1'b1;	// active low, chipselect of samsung ram

assign addr = testaddr_r;
assign chip_select = testselect_r;
assign out_enable = testoe_r;
assign write_enable = testwe_r;
assign data = testread ? data : testdata_r;

reg [3:0] count=4'h0;
always @(posedge clk_1Hz) begin
	if (start==1'b1) begin
		if (count<8) begin
			led_r = 2'b00;
			testaddr_r = taddr[count];
			testdata_r = tdata[count];
			testoe_r = 1'b1;
			testwe_r = 1'b0;
			testselect_r = 1'b0;
		end
		else begin
			testoe_r = 1'b0;
			testwe_r = 1'b1;
			testselect_r = 1'b0;
			testaddr_r = taddr[count-4'h8];
			if (testdata_r==tdata[count-4'h8]) led_r = 2'b10;
			else if (testdata_r!=tdata[count-4'h8]) led_r = 2'b01;
			else led_r = 2'b00;
		end
		count = count + 4'h1;
	end
end

endmodule